cpu.h revision 1.73.10.1
1 /* $NetBSD: cpu.h,v 1.73.10.1 2006/04/19 15:39:06 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 #ifndef _LOCORE 48 #include <sys/cpu_data.h> 49 50 #if defined(_KERNEL_OPT) 51 #include "opt_lockdebug.h" 52 #endif 53 54 struct cpu_info { 55 struct cpu_data ci_data; /* MI per-cpu data */ 56 u_long ci_cpu_freq; /* CPU frequency */ 57 u_long ci_cycles_per_hz; /* CPU freq / hz */ 58 u_long ci_divisor_delay; /* for delay/DELAY */ 59 u_long ci_divisor_recip; /* scaled reciprocal of previous; 60 see below */ 61 }; 62 63 /* 64 * To implement a more accurate microtime using the CP0 COUNT register 65 * we need to divide that register by the number of cycles per MHz. 66 * But... 67 * 68 * DIV and DIVU are expensive on MIPS (eg 75 clocks on the R4000). MULT 69 * and MULTU are only 12 clocks on the same CPU. 70 * 71 * The strategy we use is to calculate the reciprical of cycles per MHz, 72 * scaled by 1<<32. Then we can simply issue a MULTU and pluck of the 73 * HI register and have the results of the division. 74 */ 75 #define MIPS_SET_CI_RECIPRICAL(cpu) \ 76 do { \ 77 KASSERT((cpu)->ci_divisor_delay != 0); \ 78 (cpu)->ci_divisor_recip = 0x100000000ULL / (cpu)->ci_divisor_delay; \ 79 } while (0) 80 81 #define MIPS_COUNT_TO_MHZ(cpu, count, res) \ 82 asm volatile("multu %1,%2 ; mfhi %0" \ 83 : "=r"((res)) : "r"((count)), "r"((cpu)->ci_divisor_recip)) 84 85 #endif /* !_LOCORE */ 86 #endif /* _KERNEL */ 87 88 /* 89 * CTL_MACHDEP definitions. 90 */ 91 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 92 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 93 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 94 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 95 96 /* 97 * Platform can override, but note this breaks userland compatibility 98 * with other mips platforms. 99 */ 100 #ifndef CPU_MAXID 101 #define CPU_MAXID 5 /* number of valid machdep ids */ 102 103 #define CTL_MACHDEP_NAMES { \ 104 { 0, 0 }, \ 105 { "console_device", CTLTYPE_STRUCT }, \ 106 { "booted_kernel", CTLTYPE_STRING }, \ 107 { "root_device", CTLTYPE_STRING }, \ 108 { "llsc", CTLTYPE_INT }, \ 109 } 110 #endif 111 112 #ifdef _KERNEL 113 #ifdef _LKM 114 /* Assume all CPU architectures are valid for LKM's */ 115 #define MIPS1 1 116 #define MIPS3 1 117 #define MIPS4 1 118 #define MIPS32 1 119 #define MIPS64 1 120 #endif 121 122 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 123 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 124 #endif 125 126 /* Shortcut for MIPS3 or above defined */ 127 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 128 #define MIPS3_PLUS 1 129 #else 130 #undef MIPS3_PLUS 131 #endif 132 133 /* 134 * Macros to find the CPU architecture we're on at run-time, 135 * or if possible, at compile-time. 136 */ 137 138 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 139 #define CPU_ARCH_MIPS1 (1 << 0) 140 #define CPU_ARCH_MIPS2 (1 << 1) 141 #define CPU_ARCH_MIPS3 (1 << 2) 142 #define CPU_ARCH_MIPS4 (1 << 3) 143 #define CPU_ARCH_MIPS5 (1 << 4) 144 #define CPU_ARCH_MIPS32 (1 << 5) 145 #define CPU_ARCH_MIPS64 (1 << 6) 146 147 #ifndef _LOCORE 148 extern struct cpu_info cpu_info_store; 149 150 #define curcpu() (&cpu_info_store) 151 #define cpu_number() (0) 152 #define cpu_proc_fork(p1, p2) 153 154 /* XXX simonb 155 * Should the following be in a cpu_info type structure? 156 * And how many of these are per-cpu vs. per-system? (Ie, 157 * we can assume that all cpus have the same mmu-type, but 158 * maybe not that all cpus run at the same clock speed. 159 * Some SGI's apparently support R12k and R14k in the same 160 * box.) 161 */ 162 extern int cpu_arch; 163 extern int mips_cpu_flags; 164 extern int mips_has_r4k_mmu; 165 extern int mips_has_llsc; 166 extern int mips3_pg_cached; 167 168 #define CPU_MIPS_R4K_MMU 0x0001 169 #define CPU_MIPS_NO_LLSC 0x0002 170 #define CPU_MIPS_CAUSE_IV 0x0004 171 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 172 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 173 #define CPU_MIPS_CACHED_CCA_SHIFT 4 174 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 175 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 176 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 177 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 178 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 179 #define MIPS_NOT_SUPP 0x8000 180 181 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1 182 #ifdef MIPS1 183 # define CPUISMIPS3 0 184 # define CPUIS64BITS 0 185 # define CPUISMIPS32 0 186 # define CPUISMIPS64 0 187 # define CPUISMIPSNN 0 188 # define MIPS_HAS_R4K_MMU 0 189 # define MIPS_HAS_CLOCK 0 190 # define MIPS_HAS_LLSC 0 191 #endif /* MIPS1 */ 192 193 #if defined(MIPS3) || defined(MIPS4) 194 # define CPUISMIPS3 1 195 # define CPUIS64BITS 1 196 # define CPUISMIPS32 0 197 # define CPUISMIPS64 0 198 # define CPUISMIPSNN 0 199 # define MIPS_HAS_R4K_MMU 1 200 # define MIPS_HAS_CLOCK 1 201 # define MIPS_HAS_LLSC (mips_has_llsc) 202 #endif /* MIPS3 || MIPS4 */ 203 204 #ifdef MIPS32 205 # define CPUISMIPS3 1 206 # define CPUIS64BITS 0 207 # define CPUISMIPS32 1 208 # define CPUISMIPS64 0 209 # define CPUISMIPSNN 1 210 # define MIPS_HAS_R4K_MMU 1 211 # define MIPS_HAS_CLOCK 1 212 # define MIPS_HAS_LLSC 1 213 #endif /* MIPS32 */ 214 215 #ifdef MIPS64 216 # define CPUISMIPS3 1 217 # define CPUIS64BITS 1 218 # define CPUISMIPS32 0 219 # define CPUISMIPS64 1 220 # define CPUISMIPSNN 1 221 # define MIPS_HAS_R4K_MMU 1 222 # define MIPS_HAS_CLOCK 1 223 # define MIPS_HAS_LLSC 1 224 #endif /* MIPS64 */ 225 226 #else /* run-time test */ 227 228 #define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) 229 #define MIPS_HAS_LLSC (mips_has_llsc) 230 231 /* This test is ... rather bogus */ 232 #define CPUISMIPS3 ((cpu_arch & \ 233 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 234 235 /* And these aren't much better while the previous test exists as is... */ 236 #define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0) 237 #define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0) 238 #define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 239 #define CPUIS64BITS ((cpu_arch & \ 240 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 241 242 #define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3) 243 #endif /* run-time test */ 244 245 246 /* 247 * definitions of cpu-dependent requirements 248 * referenced in generic code 249 */ 250 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 251 252 void cpu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 253 254 /* 255 * Arguments to hardclock and gatherstats encapsulate the previous 256 * machine state in an opaque clockframe. 257 */ 258 struct clockframe { 259 int pc; /* program counter at time of interrupt */ 260 int sr; /* status register at time of interrupt */ 261 int ppl; /* previous priority level at time of interrupt */ 262 }; 263 264 /* 265 * A port must provde CLKF_USERMODE() and CLKF_BASEPRI() for use 266 * in machine-independent code. These differ on r4000 and r3000 systems; 267 * provide them in the port-dependent file that includes this one, using 268 * the macros below. 269 */ 270 271 /* mips1 versions */ 272 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 273 #define MIPS1_CLKF_BASEPRI(framep) \ 274 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENA_PREV)) == 0) 275 276 /* mips3 versions */ 277 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 278 #define MIPS3_CLKF_BASEPRI(framep) \ 279 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_IE)) == 0) 280 281 #ifdef IPL_ICU_MASK 282 #define ICU_CLKF_BASEPRI(framep) ((framep)->ppl == 0) 283 #endif 284 285 #define CLKF_PC(framep) ((framep)->pc) 286 #define CLKF_INTR(framep) (0) 287 288 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 289 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 290 #define CLKF_BASEPRI(framep) MIPS3_CLKF_BASEPRI(framep) 291 #endif 292 293 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 294 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 295 #define CLKF_BASEPRI(framep) MIPS1_CLKF_BASEPRI(framep) 296 #endif 297 298 #ifdef IPL_ICU_MASK 299 #undef CLKF_BASEPRI 300 #define CLKF_BASEPRI(framep) ICU_CLKF_BASEPRI(framep) 301 #endif 302 303 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 304 #define CLKF_USERMODE(framep) \ 305 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 306 #define CLKF_BASEPRI(framep) \ 307 ((CPUISMIPS3) ? MIPS3_CLKF_BASEPRI(framep): MIPS1_CLKF_BASEPRI(framep)) 308 #endif 309 310 /* 311 * This is used during profiling to integrate system time. It can safely 312 * assume that the process is resident. 313 */ 314 #define PROC_PC(p) \ 315 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 316 317 /* 318 * Preempt the current process if in interrupt from user mode, 319 * or after the current trap/syscall if in system mode. 320 */ 321 #define need_resched(ci) \ 322 do { \ 323 want_resched = 1; \ 324 if (curproc != NULL) \ 325 aston(curproc); \ 326 } while (/*CONSTCOND*/0) 327 328 /* 329 * Give a profiling tick to the current process when the user profiling 330 * buffer pages are invalid. On the MIPS, request an ast to send us 331 * through trap, marking the proc as needing a profiling tick. 332 */ 333 #define need_proftick(p) \ 334 do { \ 335 (p)->p_flag |= P_OWEUPC; \ 336 aston(p); \ 337 } while (/*CONSTCOND*/0) 338 339 /* 340 * Notify the current process (p) that it has a signal pending, 341 * process as soon as possible. 342 */ 343 #define signotify(p) aston(p) 344 345 #define aston(p) ((p)->p_md.md_astpending = 1) 346 347 extern int want_resched; /* resched() was called */ 348 349 /* 350 * Misc prototypes and variable declarations. 351 */ 352 struct lwp; 353 struct user; 354 355 extern struct lwp *fpcurlwp; /* the current FPU owner */ 356 extern struct pcb *curpcb; /* the current running pcb */ 357 extern struct segtab *segbase; /* current segtab base */ 358 359 /* trap.c */ 360 void netintr(void); 361 int kdbpeek(vaddr_t); 362 363 /* mips_machdep.c */ 364 void dumpsys(void); 365 int savectx(struct user *); 366 void mips_init_msgbuf(void); 367 void savefpregs(struct lwp *); 368 void loadfpregs(struct lwp *); 369 370 /* locore*.S */ 371 int badaddr(void *, size_t); 372 int badaddr64(uint64_t, size_t); 373 374 /* mips_machdep.c */ 375 void cpu_identify(void); 376 void mips_vector_init(void); 377 378 #endif /* ! _LOCORE */ 379 #endif /* _KERNEL */ 380 #endif /* _CPU_H_ */ 381
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