cpu.h revision 1.79
1 /* $NetBSD: cpu.h,v 1.79 2007/02/16 02:53:48 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 #ifndef _LOCORE 48 #include <sys/cpu_data.h> 49 50 #if defined(_KERNEL_OPT) 51 #include "opt_lockdebug.h" 52 #endif 53 54 struct cpu_info { 55 struct cpu_data ci_data; /* MI per-cpu data */ 56 u_long ci_cpu_freq; /* CPU frequency */ 57 u_long ci_cycles_per_hz; /* CPU freq / hz */ 58 u_long ci_divisor_delay; /* for delay/DELAY */ 59 u_long ci_divisor_recip; /* scaled reciprocal of previous; 60 see below */ 61 int ci_mtx_count; /* negative count of held mutexes */ 62 int ci_mtx_oldspl; /* saved SPL value */ 63 }; 64 65 /* 66 * To implement a more accurate microtime using the CP0 COUNT register 67 * we need to divide that register by the number of cycles per MHz. 68 * But... 69 * 70 * DIV and DIVU are expensive on MIPS (eg 75 clocks on the R4000). MULT 71 * and MULTU are only 12 clocks on the same CPU. 72 * 73 * The strategy we use is to calculate the reciprical of cycles per MHz, 74 * scaled by 1<<32. Then we can simply issue a MULTU and pluck of the 75 * HI register and have the results of the division. 76 */ 77 #define MIPS_SET_CI_RECIPRICAL(cpu) \ 78 do { \ 79 KASSERT((cpu)->ci_divisor_delay != 0); \ 80 (cpu)->ci_divisor_recip = 0x100000000ULL / (cpu)->ci_divisor_delay; \ 81 } while (0) 82 83 #define MIPS_COUNT_TO_MHZ(cpu, count, res) \ 84 __asm volatile("multu %1,%2 ; mfhi %0" \ 85 : "=r"((res)) : "r"((count)), "r"((cpu)->ci_divisor_recip)) 86 87 #endif /* !_LOCORE */ 88 #endif /* _KERNEL */ 89 90 /* 91 * CTL_MACHDEP definitions. 92 */ 93 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 94 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 95 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 96 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 97 98 /* 99 * Platform can override, but note this breaks userland compatibility 100 * with other mips platforms. 101 */ 102 #ifndef CPU_MAXID 103 #define CPU_MAXID 5 /* number of valid machdep ids */ 104 105 #define CTL_MACHDEP_NAMES { \ 106 { 0, 0 }, \ 107 { "console_device", CTLTYPE_STRUCT }, \ 108 { "booted_kernel", CTLTYPE_STRING }, \ 109 { "root_device", CTLTYPE_STRING }, \ 110 { "llsc", CTLTYPE_INT }, \ 111 } 112 #endif 113 114 #ifdef _KERNEL 115 #ifdef _LKM 116 /* Assume all CPU architectures are valid for LKM's */ 117 #define MIPS1 1 118 #define MIPS3 1 119 #define MIPS4 1 120 #define MIPS32 1 121 #define MIPS64 1 122 #endif 123 124 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 125 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 126 #endif 127 128 /* Shortcut for MIPS3 or above defined */ 129 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 130 #define MIPS3_PLUS 1 131 #else 132 #undef MIPS3_PLUS 133 #endif 134 135 /* 136 * Macros to find the CPU architecture we're on at run-time, 137 * or if possible, at compile-time. 138 */ 139 140 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 141 #define CPU_ARCH_MIPS1 (1 << 0) 142 #define CPU_ARCH_MIPS2 (1 << 1) 143 #define CPU_ARCH_MIPS3 (1 << 2) 144 #define CPU_ARCH_MIPS4 (1 << 3) 145 #define CPU_ARCH_MIPS5 (1 << 4) 146 #define CPU_ARCH_MIPS32 (1 << 5) 147 #define CPU_ARCH_MIPS64 (1 << 6) 148 149 #ifndef _LOCORE 150 extern struct cpu_info cpu_info_store; 151 152 #define curcpu() (&cpu_info_store) 153 #define cpu_number() (0) 154 #define cpu_proc_fork(p1, p2) 155 156 /* XXX simonb 157 * Should the following be in a cpu_info type structure? 158 * And how many of these are per-cpu vs. per-system? (Ie, 159 * we can assume that all cpus have the same mmu-type, but 160 * maybe not that all cpus run at the same clock speed. 161 * Some SGI's apparently support R12k and R14k in the same 162 * box.) 163 */ 164 extern int cpu_arch; 165 extern int mips_cpu_flags; 166 extern int mips_has_r4k_mmu; 167 extern int mips_has_llsc; 168 extern int mips3_pg_cached; 169 extern u_int mips3_pg_shift; 170 171 #define CPU_MIPS_R4K_MMU 0x0001 172 #define CPU_MIPS_NO_LLSC 0x0002 173 #define CPU_MIPS_CAUSE_IV 0x0004 174 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 175 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 176 #define CPU_MIPS_CACHED_CCA_SHIFT 4 177 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 178 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 179 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 180 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 181 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 182 #define MIPS_NOT_SUPP 0x8000 183 184 #endif /* !_LOCORE */ 185 186 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE) 187 188 #if defined(MIPS1) 189 190 # define CPUISMIPS3 0 191 # define CPUIS64BITS 0 192 # define CPUISMIPS32 0 193 # define CPUISMIPS64 0 194 # define CPUISMIPSNN 0 195 # define MIPS_HAS_R4K_MMU 0 196 # define MIPS_HAS_CLOCK 0 197 # define MIPS_HAS_LLSC 0 198 199 #elif defined(MIPS3) || defined(MIPS4) 200 201 # define CPUISMIPS3 1 202 # define CPUIS64BITS 1 203 # define CPUISMIPS32 0 204 # define CPUISMIPS64 0 205 # define CPUISMIPSNN 0 206 # define MIPS_HAS_R4K_MMU 1 207 # define MIPS_HAS_CLOCK 1 208 # if defined(_LOCORE) 209 # if !defined(MIPS3_5900) && !defined(MIPS3_4100) 210 # define MIPS_HAS_LLSC 1 211 # else 212 # define MIPS_HAS_LLSC 0 213 # endif 214 # else /* _LOCORE */ 215 # define MIPS_HAS_LLSC (mips_has_llsc) 216 # endif /* _LOCORE */ 217 218 #elif defined(MIPS32) 219 220 # define CPUISMIPS3 1 221 # define CPUIS64BITS 0 222 # define CPUISMIPS32 1 223 # define CPUISMIPS64 0 224 # define CPUISMIPSNN 1 225 # define MIPS_HAS_R4K_MMU 1 226 # define MIPS_HAS_CLOCK 1 227 # define MIPS_HAS_LLSC 1 228 229 #elif define(MIPS64) 230 231 # define CPUISMIPS3 1 232 # define CPUIS64BITS 1 233 # define CPUISMIPS32 0 234 # define CPUISMIPS64 1 235 # define CPUISMIPSNN 1 236 # define MIPS_HAS_R4K_MMU 1 237 # define MIPS_HAS_CLOCK 1 238 # define MIPS_HAS_LLSC 1 239 240 #endif 241 242 #else /* run-time test */ 243 244 #ifndef _LOCORE 245 246 #define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) 247 #define MIPS_HAS_LLSC (mips_has_llsc) 248 249 /* This test is ... rather bogus */ 250 #define CPUISMIPS3 ((cpu_arch & \ 251 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 252 253 /* And these aren't much better while the previous test exists as is... */ 254 #define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0) 255 #define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0) 256 #define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 257 #define CPUIS64BITS ((cpu_arch & \ 258 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 259 260 #define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3) 261 262 #else /* !_LOCORE */ 263 264 #define MIPS_HAS_LLSC 0 265 266 #endif /* !_LOCORE */ 267 268 #endif /* run-time test */ 269 270 #ifndef _LOCORE 271 272 /* 273 * definitions of cpu-dependent requirements 274 * referenced in generic code 275 */ 276 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 277 278 void cpu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 279 280 /* 281 * Arguments to hardclock and gatherstats encapsulate the previous 282 * machine state in an opaque clockframe. 283 */ 284 struct clockframe { 285 int pc; /* program counter at time of interrupt */ 286 int sr; /* status register at time of interrupt */ 287 int ppl; /* previous priority level at time of interrupt */ 288 }; 289 290 /* 291 * A port must provde CLKF_USERMODE() for use in machine-independent code. 292 * These differ on r4000 and r3000 systems; provide them in the 293 * port-dependent file that includes this one, using the macros below. 294 */ 295 296 /* mips1 versions */ 297 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 298 299 /* mips3 versions */ 300 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 301 302 #define CLKF_PC(framep) ((framep)->pc) 303 #define CLKF_INTR(framep) (0) 304 305 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 306 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 307 #endif 308 309 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 310 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 311 #endif 312 313 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 314 #define CLKF_USERMODE(framep) \ 315 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 316 #endif 317 318 /* 319 * This is used during profiling to integrate system time. It can safely 320 * assume that the process is resident. 321 */ 322 #define PROC_PC(p) \ 323 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 324 325 /* 326 * Preempt the current process if in interrupt from user mode, 327 * or after the current trap/syscall if in system mode. 328 */ 329 #define cpu_need_resched(ci) \ 330 do { \ 331 want_resched = 1; \ 332 if (curlwp != NULL) \ 333 aston(curlwp); \ 334 } while (/*CONSTCOND*/0) 335 336 /* 337 * Give a profiling tick to the current process when the user profiling 338 * buffer pages are invalid. On the MIPS, request an ast to send us 339 * through trap, marking the proc as needing a profiling tick. 340 */ 341 #define cpu_need_proftick(l) \ 342 do { \ 343 (l)->l_pflag |= LP_OWEUPC; \ 344 aston(l); \ 345 } while (/*CONSTCOND*/0) 346 347 /* 348 * Notify the current process (p) that it has a signal pending, 349 * process as soon as possible. 350 */ 351 #define cpu_signotify(p) aston(l) 352 353 #define aston(l) ((l)->l_md.md_astpending = 1) 354 355 extern int want_resched; /* resched() was called */ 356 357 /* 358 * Misc prototypes and variable declarations. 359 */ 360 struct lwp; 361 struct user; 362 363 extern struct lwp *fpcurlwp; /* the current FPU owner */ 364 extern struct pcb *curpcb; /* the current running pcb */ 365 extern struct segtab *segbase; /* current segtab base */ 366 367 /* trap.c */ 368 void netintr(void); 369 int kdbpeek(vaddr_t); 370 371 /* mips_machdep.c */ 372 void dumpsys(void); 373 int savectx(struct user *); 374 void mips_init_msgbuf(void); 375 void savefpregs(struct lwp *); 376 void loadfpregs(struct lwp *); 377 378 /* locore*.S */ 379 int badaddr(void *, size_t); 380 int badaddr64(uint64_t, size_t); 381 382 /* mips_machdep.c */ 383 void cpu_identify(void); 384 void mips_vector_init(void); 385 386 #endif /* ! _LOCORE */ 387 #endif /* _KERNEL */ 388 #endif /* _CPU_H_ */ 389
Indexes created Tue Sep 23 07:09:52 GMT 2025