cpu.h revision 1.84
1 /* $NetBSD: cpu.h,v 1.84 2007/10/17 19:55:36 garbled Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 #ifndef _LOCORE 48 #include <sys/cpu_data.h> 49 50 #if defined(_KERNEL_OPT) 51 #include "opt_lockdebug.h" 52 #endif 53 54 struct cpu_info { 55 struct cpu_data ci_data; /* MI per-cpu data */ 56 cpuid_t ci_cpuid; 57 u_long ci_cpu_freq; /* CPU frequency */ 58 u_long ci_cycles_per_hz; /* CPU freq / hz */ 59 u_long ci_divisor_delay; /* for delay/DELAY */ 60 u_long ci_divisor_recip; /* scaled reciprocal of previous; 61 see below */ 62 struct lwp *ci_curlwp; /* currently running lwp */ 63 struct lwp *ci_fpcurlwp; /* the current FPU owner */ 64 int ci_want_resched; /* user preemption pending */ 65 int ci_mtx_count; /* negative count of held mutexes */ 66 int ci_mtx_oldspl; /* saved SPL value */ 67 }; 68 69 /* 70 * To implement a more accurate microtime using the CP0 COUNT register 71 * we need to divide that register by the number of cycles per MHz. 72 * But... 73 * 74 * DIV and DIVU are expensive on MIPS (eg 75 clocks on the R4000). MULT 75 * and MULTU are only 12 clocks on the same CPU. 76 * 77 * The strategy we use is to calculate the reciprical of cycles per MHz, 78 * scaled by 1<<32. Then we can simply issue a MULTU and pluck of the 79 * HI register and have the results of the division. 80 */ 81 #define MIPS_SET_CI_RECIPRICAL(cpu) \ 82 do { \ 83 KASSERT((cpu)->ci_divisor_delay != 0); \ 84 (cpu)->ci_divisor_recip = 0x100000000ULL / (cpu)->ci_divisor_delay; \ 85 } while (0) 86 87 #define MIPS_COUNT_TO_MHZ(cpu, count, res) \ 88 __asm volatile("multu %1,%2 ; mfhi %0" \ 89 : "=r"((res)) : "r"((count)), "r"((cpu)->ci_divisor_recip)) 90 91 #endif /* !_LOCORE */ 92 #endif /* _KERNEL */ 93 94 /* 95 * CTL_MACHDEP definitions. 96 */ 97 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 98 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 99 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 100 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 101 102 /* 103 * Platform can override, but note this breaks userland compatibility 104 * with other mips platforms. 105 */ 106 #ifndef CPU_MAXID 107 #define CPU_MAXID 5 /* number of valid machdep ids */ 108 109 #define CTL_MACHDEP_NAMES { \ 110 { 0, 0 }, \ 111 { "console_device", CTLTYPE_STRUCT }, \ 112 { "booted_kernel", CTLTYPE_STRING }, \ 113 { "root_device", CTLTYPE_STRING }, \ 114 { "llsc", CTLTYPE_INT }, \ 115 } 116 #endif 117 118 #ifdef _KERNEL 119 #ifdef _LKM 120 /* Assume all CPU architectures are valid for LKM's */ 121 #define MIPS1 1 122 #define MIPS3 1 123 #define MIPS4 1 124 #define MIPS32 1 125 #define MIPS64 1 126 #endif 127 128 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 129 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 130 #endif 131 132 /* Shortcut for MIPS3 or above defined */ 133 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 134 #define MIPS3_PLUS 1 135 #else 136 #undef MIPS3_PLUS 137 #endif 138 139 /* 140 * Macros to find the CPU architecture we're on at run-time, 141 * or if possible, at compile-time. 142 */ 143 144 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 145 #define CPU_ARCH_MIPS1 (1 << 0) 146 #define CPU_ARCH_MIPS2 (1 << 1) 147 #define CPU_ARCH_MIPS3 (1 << 2) 148 #define CPU_ARCH_MIPS4 (1 << 3) 149 #define CPU_ARCH_MIPS5 (1 << 4) 150 #define CPU_ARCH_MIPS32 (1 << 5) 151 #define CPU_ARCH_MIPS64 (1 << 6) 152 153 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 154 #define MIPS_CURLWP $23 155 #define MIPS_CURLWP_QUOTED "$23" 156 #define MIPS_CURLWP_CARD 23 157 #define MIPS_CURLWP_FRAME(x) FRAME_S7(x) 158 159 #ifndef _LOCORE 160 161 extern struct cpu_info cpu_info_store; 162 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 163 164 #define curlwp mips_curlwp 165 #define curcpu() (curlwp->l_cpu) 166 #define curpcb ((struct pcb *)curlwp->l_addr) 167 #define fpcurlwp (curcpu()->ci_fpcurlwp) 168 #define cpu_number() (0) 169 #define cpu_proc_fork(p1, p2) 170 171 /* XXX simonb 172 * Should the following be in a cpu_info type structure? 173 * And how many of these are per-cpu vs. per-system? (Ie, 174 * we can assume that all cpus have the same mmu-type, but 175 * maybe not that all cpus run at the same clock speed. 176 * Some SGI's apparently support R12k and R14k in the same 177 * box.) 178 */ 179 extern int cpu_arch; 180 extern int mips_cpu_flags; 181 extern int mips_has_r4k_mmu; 182 extern int mips_has_llsc; 183 extern int mips3_pg_cached; 184 extern u_int mips3_pg_shift; 185 186 #define CPU_MIPS_R4K_MMU 0x0001 187 #define CPU_MIPS_NO_LLSC 0x0002 188 #define CPU_MIPS_CAUSE_IV 0x0004 189 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 190 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 191 #define CPU_MIPS_CACHED_CCA_SHIFT 4 192 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 193 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 194 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 195 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 196 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 197 #define MIPS_NOT_SUPP 0x8000 198 199 #endif /* !_LOCORE */ 200 201 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE) 202 203 #if defined(MIPS1) 204 205 # define CPUISMIPS3 0 206 # define CPUIS64BITS 0 207 # define CPUISMIPS32 0 208 # define CPUISMIPS64 0 209 # define CPUISMIPSNN 0 210 # define MIPS_HAS_R4K_MMU 0 211 # define MIPS_HAS_CLOCK 0 212 # define MIPS_HAS_LLSC 0 213 214 #elif defined(MIPS3) || defined(MIPS4) 215 216 # define CPUISMIPS3 1 217 # define CPUIS64BITS 1 218 # define CPUISMIPS32 0 219 # define CPUISMIPS64 0 220 # define CPUISMIPSNN 0 221 # define MIPS_HAS_R4K_MMU 1 222 # define MIPS_HAS_CLOCK 1 223 # if defined(_LOCORE) 224 # if !defined(MIPS3_5900) && !defined(MIPS3_4100) 225 # define MIPS_HAS_LLSC 1 226 # else 227 # define MIPS_HAS_LLSC 0 228 # endif 229 # else /* _LOCORE */ 230 # define MIPS_HAS_LLSC (mips_has_llsc) 231 # endif /* _LOCORE */ 232 233 #elif defined(MIPS32) 234 235 # define CPUISMIPS3 1 236 # define CPUIS64BITS 0 237 # define CPUISMIPS32 1 238 # define CPUISMIPS64 0 239 # define CPUISMIPSNN 1 240 # define MIPS_HAS_R4K_MMU 1 241 # define MIPS_HAS_CLOCK 1 242 # define MIPS_HAS_LLSC 1 243 244 #elif defined(MIPS64) 245 246 # define CPUISMIPS3 1 247 # define CPUIS64BITS 1 248 # define CPUISMIPS32 0 249 # define CPUISMIPS64 1 250 # define CPUISMIPSNN 1 251 # define MIPS_HAS_R4K_MMU 1 252 # define MIPS_HAS_CLOCK 1 253 # define MIPS_HAS_LLSC 1 254 255 #endif 256 257 #else /* run-time test */ 258 259 #ifndef _LOCORE 260 261 #define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) 262 #define MIPS_HAS_LLSC (mips_has_llsc) 263 264 /* This test is ... rather bogus */ 265 #define CPUISMIPS3 ((cpu_arch & \ 266 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 267 268 /* And these aren't much better while the previous test exists as is... */ 269 #define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0) 270 #define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0) 271 #define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 272 #define CPUIS64BITS ((cpu_arch & \ 273 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 274 275 #define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3) 276 277 #else /* !_LOCORE */ 278 279 #define MIPS_HAS_LLSC 0 280 281 #endif /* !_LOCORE */ 282 283 #endif /* run-time test */ 284 285 #ifndef _LOCORE 286 287 /* 288 * definitions of cpu-dependent requirements 289 * referenced in generic code 290 */ 291 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 292 293 void cpu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 294 295 /* 296 * Arguments to hardclock and gatherstats encapsulate the previous 297 * machine state in an opaque clockframe. 298 */ 299 struct clockframe { 300 int pc; /* program counter at time of interrupt */ 301 int sr; /* status register at time of interrupt */ 302 int ppl; /* previous priority level at time of interrupt */ 303 }; 304 305 /* 306 * A port must provde CLKF_USERMODE() for use in machine-independent code. 307 * These differ on r4000 and r3000 systems; provide them in the 308 * port-dependent file that includes this one, using the macros below. 309 */ 310 311 /* mips1 versions */ 312 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 313 314 /* mips3 versions */ 315 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 316 317 #define CLKF_PC(framep) ((framep)->pc) 318 #define CLKF_INTR(framep) (0) 319 320 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 321 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 322 #endif 323 324 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 325 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 326 #endif 327 328 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 329 #define CLKF_USERMODE(framep) \ 330 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 331 #endif 332 333 /* 334 * This is used during profiling to integrate system time. It can safely 335 * assume that the process is resident. 336 */ 337 #define PROC_PC(p) \ 338 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 339 340 /* 341 * Preempt the current process if in interrupt from user mode, 342 * or after the current trap/syscall if in system mode. 343 */ 344 void cpu_need_resched(struct cpu_info *, int); 345 346 /* 347 * Give a profiling tick to the current process when the user profiling 348 * buffer pages are invalid. On the MIPS, request an ast to send us 349 * through trap, marking the proc as needing a profiling tick. 350 */ 351 #define cpu_need_proftick(l) \ 352 do { \ 353 (l)->l_pflag |= LP_OWEUPC; \ 354 aston(l); \ 355 } while (/*CONSTCOND*/0) 356 357 /* 358 * Notify the current lwp (l) that it has a signal pending, 359 * process as soon as possible. 360 */ 361 #define cpu_signotify(l) aston(l) 362 363 #define aston(l) ((l)->l_md.md_astpending = 1) 364 365 /* 366 * Misc prototypes and variable declarations. 367 */ 368 struct lwp; 369 struct user; 370 371 extern struct segtab *segbase; /* current segtab base */ 372 373 /* trap.c */ 374 void netintr(void); 375 int kdbpeek(vaddr_t); 376 377 /* mips_machdep.c */ 378 void dumpsys(void); 379 int savectx(struct user *); 380 void mips_init_msgbuf(void); 381 void savefpregs(struct lwp *); 382 void loadfpregs(struct lwp *); 383 384 /* locore*.S */ 385 int badaddr(void *, size_t); 386 int badaddr64(uint64_t, size_t); 387 388 /* mips_machdep.c */ 389 void cpu_identify(void); 390 void mips_vector_init(void); 391 392 #endif /* ! _LOCORE */ 393 #endif /* _KERNEL */ 394 #endif /* _CPU_H_ */ 395
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