cpu.h revision 1.90
1 /* $NetBSD: cpu.h,v 1.90 2008/05/26 15:59:29 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 #ifndef _LOCORE 48 #include <sys/cpu_data.h> 49 50 #if defined(_KERNEL_OPT) 51 #include "opt_lockdebug.h" 52 #endif 53 54 struct cpu_info { 55 struct cpu_data ci_data; /* MI per-cpu data */ 56 struct cpu_info *ci_next; /* Next CPU in list */ 57 cpuid_t ci_cpuid; /* Machine-level identifier */ 58 u_long ci_cpu_freq; /* CPU frequency */ 59 u_long ci_cycles_per_hz; /* CPU freq / hz */ 60 u_long ci_divisor_delay; /* for delay/DELAY */ 61 u_long ci_divisor_recip; /* unused, for obsolete microtime(9) */ 62 struct lwp *ci_curlwp; /* currently running lwp */ 63 struct lwp *ci_fpcurlwp; /* the current FPU owner */ 64 int ci_want_resched; /* user preemption pending */ 65 int ci_mtx_count; /* negative count of held mutexes */ 66 int ci_mtx_oldspl; /* saved SPL value */ 67 int ci_idepth; /* hardware interrupt depth */ 68 }; 69 70 #define CPU_INFO_ITERATOR int 71 #define CPU_INFO_FOREACH(cii, ci) \ 72 (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next 73 74 #endif /* !_LOCORE */ 75 #endif /* _KERNEL */ 76 77 /* 78 * CTL_MACHDEP definitions. 79 */ 80 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 81 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 82 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 83 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 84 85 /* 86 * Platform can override, but note this breaks userland compatibility 87 * with other mips platforms. 88 */ 89 #ifndef CPU_MAXID 90 #define CPU_MAXID 5 /* number of valid machdep ids */ 91 92 #endif 93 94 #ifdef _KERNEL 95 #if defined(_LKM) || defined(_STANDALONE) 96 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 97 #define MIPS1 1 98 #define MIPS3 1 99 #define MIPS4 1 100 #define MIPS32 1 101 #define MIPS64 1 102 #endif 103 104 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 105 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 106 #endif 107 108 /* Shortcut for MIPS3 or above defined */ 109 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 110 #define MIPS3_PLUS 1 111 #else 112 #undef MIPS3_PLUS 113 #endif 114 115 /* 116 * Macros to find the CPU architecture we're on at run-time, 117 * or if possible, at compile-time. 118 */ 119 120 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 121 #define CPU_ARCH_MIPS1 (1 << 0) 122 #define CPU_ARCH_MIPS2 (1 << 1) 123 #define CPU_ARCH_MIPS3 (1 << 2) 124 #define CPU_ARCH_MIPS4 (1 << 3) 125 #define CPU_ARCH_MIPS5 (1 << 4) 126 #define CPU_ARCH_MIPS32 (1 << 5) 127 #define CPU_ARCH_MIPS64 (1 << 6) 128 129 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 130 #define MIPS_CURLWP $23 131 #define MIPS_CURLWP_QUOTED "$23" 132 #define MIPS_CURLWP_CARD 23 133 #define MIPS_CURLWP_FRAME(x) FRAME_S7(x) 134 135 #ifndef _LOCORE 136 137 extern struct cpu_info cpu_info_store; 138 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 139 140 #define curlwp mips_curlwp 141 #define curcpu() (curlwp->l_cpu) 142 #define curpcb ((struct pcb *)curlwp->l_addr) 143 #define fpcurlwp (curcpu()->ci_fpcurlwp) 144 #define cpu_number() (0) 145 #define cpu_proc_fork(p1, p2) 146 147 /* XXX simonb 148 * Should the following be in a cpu_info type structure? 149 * And how many of these are per-cpu vs. per-system? (Ie, 150 * we can assume that all cpus have the same mmu-type, but 151 * maybe not that all cpus run at the same clock speed. 152 * Some SGI's apparently support R12k and R14k in the same 153 * box.) 154 */ 155 extern int cpu_arch; 156 extern int mips_cpu_flags; 157 extern int mips_has_r4k_mmu; 158 extern int mips_has_llsc; 159 extern int mips3_pg_cached; 160 extern u_int mips3_pg_shift; 161 162 #define CPU_MIPS_R4K_MMU 0x0001 163 #define CPU_MIPS_NO_LLSC 0x0002 164 #define CPU_MIPS_CAUSE_IV 0x0004 165 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 166 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 167 #define CPU_MIPS_CACHED_CCA_SHIFT 4 168 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 169 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 170 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 171 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 172 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 173 #define MIPS_NOT_SUPP 0x8000 174 175 #endif /* !_LOCORE */ 176 177 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE) 178 179 #if defined(MIPS1) 180 181 # define CPUISMIPS3 0 182 # define CPUIS64BITS 0 183 # define CPUISMIPS32 0 184 # define CPUISMIPS64 0 185 # define CPUISMIPSNN 0 186 # define MIPS_HAS_R4K_MMU 0 187 # define MIPS_HAS_CLOCK 0 188 # define MIPS_HAS_LLSC 0 189 190 #elif defined(MIPS3) || defined(MIPS4) 191 192 # define CPUISMIPS3 1 193 # define CPUIS64BITS 1 194 # define CPUISMIPS32 0 195 # define CPUISMIPS64 0 196 # define CPUISMIPSNN 0 197 # define MIPS_HAS_R4K_MMU 1 198 # define MIPS_HAS_CLOCK 1 199 # if defined(_LOCORE) 200 # if !defined(MIPS3_5900) && !defined(MIPS3_4100) 201 # define MIPS_HAS_LLSC 1 202 # else 203 # define MIPS_HAS_LLSC 0 204 # endif 205 # else /* _LOCORE */ 206 # define MIPS_HAS_LLSC (mips_has_llsc) 207 # endif /* _LOCORE */ 208 209 #elif defined(MIPS32) 210 211 # define CPUISMIPS3 1 212 # define CPUIS64BITS 0 213 # define CPUISMIPS32 1 214 # define CPUISMIPS64 0 215 # define CPUISMIPSNN 1 216 # define MIPS_HAS_R4K_MMU 1 217 # define MIPS_HAS_CLOCK 1 218 # define MIPS_HAS_LLSC 1 219 220 #elif defined(MIPS64) 221 222 # define CPUISMIPS3 1 223 # define CPUIS64BITS 1 224 # define CPUISMIPS32 0 225 # define CPUISMIPS64 1 226 # define CPUISMIPSNN 1 227 # define MIPS_HAS_R4K_MMU 1 228 # define MIPS_HAS_CLOCK 1 229 # define MIPS_HAS_LLSC 1 230 231 #endif 232 233 #else /* run-time test */ 234 235 #ifndef _LOCORE 236 237 #define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) 238 #define MIPS_HAS_LLSC (mips_has_llsc) 239 240 /* This test is ... rather bogus */ 241 #define CPUISMIPS3 ((cpu_arch & \ 242 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 243 244 /* And these aren't much better while the previous test exists as is... */ 245 #define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0) 246 #define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0) 247 #define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 248 #define CPUIS64BITS ((cpu_arch & \ 249 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 250 251 #define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3) 252 253 #else /* !_LOCORE */ 254 255 #define MIPS_HAS_LLSC 0 256 257 #endif /* !_LOCORE */ 258 259 #endif /* run-time test */ 260 261 #ifndef _LOCORE 262 263 /* 264 * definitions of cpu-dependent requirements 265 * referenced in generic code 266 */ 267 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 268 269 void cpu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 270 271 /* 272 * Arguments to hardclock and gatherstats encapsulate the previous 273 * machine state in an opaque clockframe. 274 */ 275 struct clockframe { 276 int pc; /* program counter at time of interrupt */ 277 int sr; /* status register at time of interrupt */ 278 int ppl; /* previous priority level at time of interrupt */ 279 }; 280 281 /* 282 * A port must provde CLKF_USERMODE() for use in machine-independent code. 283 * These differ on r4000 and r3000 systems; provide them in the 284 * port-dependent file that includes this one, using the macros below. 285 */ 286 287 /* mips1 versions */ 288 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 289 290 /* mips3 versions */ 291 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 292 293 #define CLKF_PC(framep) ((framep)->pc) 294 #define CLKF_INTR(framep) (0) 295 296 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 297 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 298 #endif 299 300 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 301 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 302 #endif 303 304 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 305 #define CLKF_USERMODE(framep) \ 306 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 307 #endif 308 309 /* 310 * This is used during profiling to integrate system time. It can safely 311 * assume that the process is resident. 312 */ 313 #define PROC_PC(p) \ 314 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 315 316 /* 317 * Preempt the current process if in interrupt from user mode, 318 * or after the current trap/syscall if in system mode. 319 */ 320 void cpu_need_resched(struct cpu_info *, int); 321 322 /* 323 * Give a profiling tick to the current process when the user profiling 324 * buffer pages are invalid. On the MIPS, request an ast to send us 325 * through trap, marking the proc as needing a profiling tick. 326 */ 327 #define cpu_need_proftick(l) \ 328 do { \ 329 (l)->l_pflag |= LP_OWEUPC; \ 330 aston(l); \ 331 } while (/*CONSTCOND*/0) 332 333 /* 334 * Notify the current lwp (l) that it has a signal pending, 335 * process as soon as possible. 336 */ 337 #define cpu_signotify(l) aston(l) 338 339 #define aston(l) ((l)->l_md.md_astpending = 1) 340 341 /* 342 * Misc prototypes and variable declarations. 343 */ 344 struct lwp; 345 struct user; 346 347 extern struct segtab *segbase; /* current segtab base */ 348 349 /* trap.c */ 350 void netintr(void); 351 int kdbpeek(vaddr_t); 352 353 /* mips_machdep.c */ 354 void dumpsys(void); 355 int savectx(struct user *); 356 void mips_init_msgbuf(void); 357 void savefpregs(struct lwp *); 358 void loadfpregs(struct lwp *); 359 360 /* locore*.S */ 361 int badaddr(void *, size_t); 362 int badaddr64(uint64_t, size_t); 363 364 /* mips_machdep.c */ 365 void cpu_identify(void); 366 void mips_vector_init(void); 367 368 #endif /* ! _LOCORE */ 369 #endif /* _KERNEL */ 370 #endif /* _CPU_H_ */ 371
Indexes created Fri Sep 26 08:10:20 GMT 2025