cpu.h revision 1.90.16.11
1 /* $NetBSD: cpu.h,v 1.90.16.11 2010/01/14 00:40:35 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 #ifndef _LOCORE 48 #include <sys/cpu_data.h> 49 #include <sys/device.h> 50 51 #if defined(_KERNEL_OPT) 52 #include "opt_lockdebug.h" 53 #include "opt_multiprocessor.h" 54 #endif 55 56 struct pridtab { 57 int cpu_cid; 58 int cpu_pid; 59 int cpu_rev; /* -1 == wildcard */ 60 int cpu_copts; /* -1 == wildcard */ 61 int cpu_isa; /* -1 == probed (mips32/mips64) */ 62 int cpu_ntlb; /* -1 == unknown, 0 == probed */ 63 int cpu_flags; 64 u_int cpu_cp0flags; /* presence of some cp0 regs */ 65 u_int cpu_cidflags; /* company-specific flags */ 66 const char *cpu_name; 67 }; 68 69 extern const struct pridtab *mycpu; 70 71 /* 72 * bitfield defines for cpu_cp0flags 73 */ 74 #define MIPS_CP0FL_USE __BIT(0) /* use these flags */ 75 #define MIPS_CP0FL_ECC __BIT(1) 76 #define MIPS_CP0FL_CACHE_ERR __BIT(2) 77 #define MIPS_CP0FL_EIRR __BIT(3) 78 #define MIPS_CP0FL_EIMR __BIT(4) 79 #define MIPS_CP0FL_EBASE __BIT(5) 80 #define MIPS_CP0FL_CONFIG __BIT(6) 81 #define MIPS_CP0FL_CONFIGn(n) (__BIT(7) << ((n) & 7)) 82 83 /* 84 * cpu_cidflags defines, by company 85 */ 86 /* 87 * RMI company-specific cpu_cidflags 88 */ 89 #define MIPS_CIDFL_RMI_TYPE __BITS(2,0) 90 # define CIDFL_RMI_TYPE_XLR 0 91 # define CIDFL_RMI_TYPE_XLS 1 92 # define CIDFL_RMI_TYPE_XLP 2 93 #define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3) 94 # define MIPS_CIDFL_RMI_THREADS_SHIFT 3 95 #define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7) 96 # define MIPS_CIDFL_RMI_CORES_SHIFT 7 97 # define LOG2_1 0 98 # define LOG2_2 1 99 # define LOG2_4 2 100 # define LOG2_8 3 101 # define MIPS_CIDFL_RMI_CPUS(ncores, nthreads) \ 102 ((LOG2_ ## ncores << MIPS_CIDFL_RMI_CORES_SHIFT) \ 103 |(LOG2_ ## nthreads << MIPS_CIDFL_RMI_THREADS_SHIFT)) 104 # define MIPS_CIDFL_RMI_NTHREADS(cidfl) \ 105 (1 << (((cidfl) & MIPS_CIDFL_RMI_THREADS_MASK) \ 106 >> MIPS_CIDFL_RMI_THREADS_SHIFT)) 107 # define MIPS_CIDFL_RMI_NCORES(cidfl) \ 108 (1 << (((cidfl) & MIPS_CIDFL_RMI_CORES_MASK) \ 109 >> MIPS_CIDFL_RMI_CORES_SHIFT)) 110 #define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11) 111 # define MIPS_CIDFL_RMI_L2SZ_SHIFT 11 112 # define RMI_L2SZ_256KB 0 113 # define RMI_L2SZ_512KB 1 114 # define RMI_L2SZ_1MB 2 115 # define RMI_L2SZ_2MB 3 116 # define RMI_L2SZ_4MB 4 117 # define MIPS_CIDFL_RMI_L2(l2sz) \ 118 (RMI_L2SZ_ ## l2sz << MIPS_CIDFL_RMI_L2SZ_SHIFT) 119 # define MIPS_CIDFL_RMI_L2SZ(cidfl) \ 120 ((256*1024) << (((cidfl) & MIPS_CIDFL_RMI_L2SZ_MASK) \ 121 >> MIPS_CIDFL_RMI_L2SZ_SHIFT)) 122 123 124 125 struct cpu_info { 126 struct cpu_data ci_data; /* MI per-cpu data */ 127 struct cpu_info *ci_next; /* Next CPU in list */ 128 cpuid_t ci_cpuid; /* Machine-level identifier */ 129 u_long ci_cpu_freq; /* CPU frequency */ 130 u_long ci_cycles_per_hz; /* CPU freq / hz */ 131 u_long ci_divisor_delay; /* for delay/DELAY */ 132 u_long ci_divisor_recip; /* unused, for obsolete microtime(9) */ 133 struct lwp *ci_curlwp; /* currently running lwp */ 134 struct lwp *ci_fpcurlwp; /* the current FPU owner */ 135 int ci_want_resched; /* user preemption pending */ 136 int ci_mtx_count; /* negative count of held mutexes */ 137 int ci_mtx_oldspl; /* saved SPL value */ 138 int ci_idepth; /* hardware interrupt depth */ 139 device_t ci_dev; /* owning device */ 140 vaddr_t ci_ebase; /* VA of exception base */ 141 paddr_t ci_ebase_pa; /* PA of exception base */ 142 }; 143 144 #define CPU_INFO_ITERATOR int 145 #define CPU_INFO_FOREACH(cii, ci) \ 146 (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next 147 148 #endif /* !_LOCORE */ 149 #endif /* _KERNEL */ 150 151 /* 152 * CTL_MACHDEP definitions. 153 */ 154 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 155 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 156 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 157 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 158 159 /* 160 * Platform can override, but note this breaks userland compatibility 161 * with other mips platforms. 162 */ 163 #ifndef CPU_MAXID 164 #define CPU_MAXID 5 /* number of valid machdep ids */ 165 166 #endif 167 168 #ifdef _KERNEL 169 #if defined(_LKM) || defined(_STANDALONE) 170 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 171 #define MIPS1 1 172 #define MIPS3 1 173 #define MIPS4 1 174 #define MIPS32 1 175 #define MIPS64 1 176 #endif 177 178 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 179 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 180 #endif 181 182 /* Shortcut for MIPS3 or above defined */ 183 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 184 #define MIPS3_PLUS 1 185 #else 186 #undef MIPS3_PLUS 187 #endif 188 189 /* 190 * Macros to find the CPU architecture we're on at run-time, 191 * or if possible, at compile-time. 192 */ 193 194 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 195 #define CPU_ARCH_MIPS1 (1 << 0) 196 #define CPU_ARCH_MIPS2 (1 << 1) 197 #define CPU_ARCH_MIPS3 (1 << 2) 198 #define CPU_ARCH_MIPS4 (1 << 3) 199 #define CPU_ARCH_MIPS5 (1 << 4) 200 #define CPU_ARCH_MIPS32 (1 << 5) 201 #define CPU_ARCH_MIPS64 (1 << 6) 202 203 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 204 #define MIPS_CURLWP $23 205 #define MIPS_CURLWP_QUOTED "$23" 206 #define MIPS_CURLWP_CARD 23 207 #define MIPS_CURLWP_FRAME(x) FRAME_S7(x) 208 209 #ifndef _LOCORE 210 211 extern struct cpu_info cpu_info_store; 212 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 213 214 #define curlwp mips_curlwp 215 #define curcpu() (curlwp->l_cpu) 216 #define curpcb ((struct pcb *)curlwp->l_addr) 217 #define fpcurlwp (curcpu()->ci_fpcurlwp) 218 #define cpu_number() (0) 219 #define cpu_proc_fork(p1, p2) ((void)((p2)->p_md.md_abi = (p1)->p_md.md_abi)) 220 221 /* XXX simonb 222 * Should the following be in a cpu_info type structure? 223 * And how many of these are per-cpu vs. per-system? (Ie, 224 * we can assume that all cpus have the same mmu-type, but 225 * maybe not that all cpus run at the same clock speed. 226 * Some SGI's apparently support R12k and R14k in the same 227 * box.) 228 */ 229 extern int cpu_arch; 230 extern int mips_cpu_flags; 231 extern int mips_has_r4k_mmu; 232 extern int mips_has_llsc; 233 extern int mips3_pg_cached; 234 #ifdef _LP64 235 extern uint64_t mips3_xkphys_cached; 236 #endif 237 extern u_int mips3_pg_shift; 238 239 #define CPU_MIPS_R4K_MMU 0x0001 240 #define CPU_MIPS_NO_LLSC 0x0002 241 #define CPU_MIPS_CAUSE_IV 0x0004 242 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 243 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 244 #define CPU_MIPS_CACHED_CCA_SHIFT 4 245 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 246 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 247 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 248 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 249 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 250 #define CPU_MIPS_NO_LLADDR 0x1000 251 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 252 #define MIPS_NOT_SUPP 0x8000 253 254 #endif /* !_LOCORE */ 255 256 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE) 257 258 #if defined(MIPS1) 259 260 # define CPUISMIPS3 0 261 # define CPUIS64BITS 0 262 # define CPUISMIPS32 0 263 # define CPUISMIPS64 0 264 # define CPUISMIPSNN 0 265 # define MIPS_HAS_R4K_MMU 0 266 # define MIPS_HAS_CLOCK 0 267 # define MIPS_HAS_LLSC 0 268 # define MIPS_HAS_LLADDR 0 269 270 #elif defined(MIPS3) || defined(MIPS4) 271 272 # define CPUISMIPS3 1 273 # define CPUIS64BITS 1 274 # define CPUISMIPS32 0 275 # define CPUISMIPS64 0 276 # define CPUISMIPSNN 0 277 # define MIPS_HAS_R4K_MMU 1 278 # define MIPS_HAS_CLOCK 1 279 # if defined(_LOCORE) 280 # if !defined(MIPS3_5900) && !defined(MIPS3_4100) 281 # define MIPS_HAS_LLSC 1 282 # else 283 # define MIPS_HAS_LLSC 0 284 # endif 285 # else /* _LOCORE */ 286 # define MIPS_HAS_LLSC (mips_has_llsc) 287 # endif /* _LOCORE */ 288 # define MIPS_HAS_LLADDR ((mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 289 290 #elif defined(MIPS32) 291 292 # define CPUISMIPS3 1 293 # define CPUIS64BITS 0 294 # define CPUISMIPS32 1 295 # define CPUISMIPS64 0 296 # define CPUISMIPSNN 1 297 # define MIPS_HAS_R4K_MMU 1 298 # define MIPS_HAS_CLOCK 1 299 # define MIPS_HAS_LLSC 1 300 # define MIPS_HAS_LLADDR ((mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 301 302 #elif defined(MIPS64) 303 304 # define CPUISMIPS3 1 305 # define CPUIS64BITS 1 306 # define CPUISMIPS32 0 307 # define CPUISMIPS64 1 308 # define CPUISMIPSNN 1 309 # define MIPS_HAS_R4K_MMU 1 310 # define MIPS_HAS_CLOCK 1 311 # define MIPS_HAS_LLSC 1 312 # define MIPS_HAS_LLADDR ((mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 313 314 #endif 315 316 #else /* run-time test */ 317 318 #ifndef _LOCORE 319 320 #define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) 321 #define MIPS_HAS_LLSC (mips_has_llsc) 322 #define MIPS_HAS_LLADDR ((mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 323 324 /* This test is ... rather bogus */ 325 #define CPUISMIPS3 ((cpu_arch & \ 326 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 327 328 /* And these aren't much better while the previous test exists as is... */ 329 #define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0) 330 #define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0) 331 #define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 332 #define CPUIS64BITS ((cpu_arch & \ 333 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 334 335 #define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3) 336 337 #else /* !_LOCORE */ 338 339 #define MIPS_HAS_LLSC 0 340 341 #endif /* !_LOCORE */ 342 343 #endif /* run-time test */ 344 345 #ifndef _LOCORE 346 347 /* 348 * definitions of cpu-dependent requirements 349 * referenced in generic code 350 */ 351 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 352 353 void cpu_intr(uint32_t, uint32_t, vaddr_t, uint32_t); 354 355 /* 356 * Arguments to hardclock and gatherstats encapsulate the previous 357 * machine state in an opaque clockframe. 358 */ 359 struct clockframe { 360 vaddr_t pc; /* program counter at time of interrupt */ 361 uint32_t sr; /* status register at time of interrupt */ 362 u_int ppl; /* previous priority level at time of interrupt */ 363 }; 364 365 /* 366 * A port must provde CLKF_USERMODE() for use in machine-independent code. 367 * These differ on r4000 and r3000 systems; provide them in the 368 * port-dependent file that includes this one, using the macros below. 369 */ 370 371 /* mips1 versions */ 372 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 373 374 /* mips3 versions */ 375 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 376 377 #define CLKF_PC(framep) ((framep)->pc) 378 #define CLKF_INTR(framep) (0) 379 380 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 381 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 382 #endif 383 384 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 385 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 386 #endif 387 388 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 389 #define CLKF_USERMODE(framep) \ 390 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 391 #endif 392 393 /* 394 * This is used during profiling to integrate system time. It can safely 395 * assume that the process is resident. 396 */ 397 #define PROC_PC(p) \ 398 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 399 400 /* 401 * Preempt the current process if in interrupt from user mode, 402 * or after the current trap/syscall if in system mode. 403 */ 404 void cpu_need_resched(struct cpu_info *, int); 405 406 /* 407 * Give a profiling tick to the current process when the user profiling 408 * buffer pages are invalid. On the MIPS, request an ast to send us 409 * through trap, marking the proc as needing a profiling tick. 410 */ 411 #define cpu_need_proftick(l) \ 412 do { \ 413 (l)->l_pflag |= LP_OWEUPC; \ 414 aston(l); \ 415 } while (/*CONSTCOND*/0) 416 417 /* 418 * Notify the current lwp (l) that it has a signal pending, 419 * process as soon as possible. 420 */ 421 #define cpu_signotify(l) aston(l) 422 423 #define aston(l) ((l)->l_md.md_astpending = 1) 424 425 /* 426 * Misc prototypes and variable declarations. 427 */ 428 struct lwp; 429 struct user; 430 431 extern struct segtab *segbase; /* current segtab base */ 432 extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */ 433 434 /* copy.S */ 435 int8_t ufetch_int8(void *); 436 int16_t ufetch_int16(void *); 437 int32_t ufetch_int32(void *); 438 uint8_t ufetch_uint8(void *); 439 uint16_t ufetch_uint16(void *); 440 uint32_t ufetch_uint32(void *); 441 int8_t ufetch_int8_intrsafe(void *); 442 int16_t ufetch_int16_intrsafe(void *); 443 int32_t ufetch_int32_intrsafe(void *); 444 uint8_t ufetch_uint8_intrsafe(void *); 445 uint16_t ufetch_uint16_intrsafe(void *); 446 uint32_t ufetch_uint32_intrsafe(void *); 447 #ifdef _LP64 448 int64_t ufetch_int64(void *); 449 uint64_t ufetch_uint64(void *); 450 int64_t ufetch_int64_intrsafe(void *); 451 uint64_t ufetch_uint64_intrsafe(void *); 452 #endif 453 char ufetch_char(void *); 454 short ufetch_short(void *); 455 int ufetch_int(void *); 456 long ufetch_long(void *); 457 char ufetch_char_intrsafe(void *); 458 short ufetch_short_intrsafe(void *); 459 int ufetch_int_intrsafe(void *); 460 long ufetch_long_intrsafe(void *); 461 462 u_char ufetch_uchar(void *); 463 u_short ufetch_ushort(void *); 464 u_int ufetch_uint(void *); 465 u_long ufetch_ulong(void *); 466 u_char ufetch_uchar_intrsafe(void *); 467 u_short ufetch_ushort_intrsafe(void *); 468 u_int ufetch_uint_intrsafe(void *); 469 u_long ufetch_ulong_intrsafe(void *); 470 void *ufetch_ptr(void *); 471 472 int ustore_int8(void *, int8_t); 473 int ustore_int16(void *, int16_t); 474 int ustore_int32(void *, int32_t); 475 int ustore_uint8(void *, uint8_t); 476 int ustore_uint16(void *, uint16_t); 477 int ustore_uint32(void *, uint32_t); 478 int ustore_int8_intrsafe(void *, int8_t); 479 int ustore_int16_intrsafe(void *, int16_t); 480 int ustore_int32_intrsafe(void *, int32_t); 481 int ustore_uint8_intrsafe(void *, uint8_t); 482 int ustore_uint16_intrsafe(void *, uint16_t); 483 int ustore_uint32_intrsafe(void *, uint32_t); 484 #ifdef _LP64 485 int ustore_int64(void *, int64_t); 486 int ustore_uint64(void *, uint64_t); 487 int ustore_int64_intrsafe(void *, int64_t); 488 int ustore_uint64_intrsafe(void *, uint64_t); 489 #endif 490 int ustore_char(void *, char); 491 int ustore_char_intrsafe(void *, char); 492 int ustore_short(void *, short); 493 int ustore_short_intrsafe(void *, short); 494 int ustore_int(void *, int); 495 int ustore_int_intrsafe(void *, int); 496 int ustore_long(void *, long); 497 int ustore_long_intrsafe(void *, long); 498 int ustore_uchar(void *, u_char); 499 int ustore_uchar_intrsafe(void *, u_char); 500 int ustore_ushort(void *, u_short); 501 int ustore_ushort_intrsafe(void *, u_short); 502 int ustore_uint(void *, u_int); 503 int ustore_uint_intrsafe(void *, u_int); 504 int ustore_ulong(void *, u_long); 505 int ustore_ulong_intrsafe(void *, u_long); 506 int ustore_ptr(void *, void *); 507 int ustore_ptr_intrsafe(void *, void *); 508 509 int ustore_uint32_isync(void *, uint32_t); 510 511 /* trap.c */ 512 void netintr(void); 513 int kdbpeek(vaddr_t); 514 515 /* mips_machdep.c */ 516 struct mips_vmfreelist; 517 struct phys_ram_seg; 518 void dumpsys(void); 519 int savectx(struct user *); 520 void mips_init_msgbuf(void); 521 void mips_init_lwp0_uarea(void); 522 void mips_page_physload(vaddr_t, vaddr_t, 523 const struct phys_ram_seg *, size_t, 524 const struct mips_vmfreelist *, size_t); 525 void savefpregs(struct lwp *); 526 void loadfpregs(struct lwp *); 527 528 /* locore*.S */ 529 int badaddr(void *, size_t); 530 int badaddr64(uint64_t, size_t); 531 532 /* mips_machdep.c */ 533 void cpu_identify(device_t); 534 void mips_vector_init(void); 535 536 #endif /* ! _LOCORE */ 537 #endif /* _KERNEL */ 538 #endif /* _CPU_H_ */ 539
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