cpu.h revision 1.90.16.15
1 /* $NetBSD: cpu.h,v 1.90.16.15 2010/01/26 21:19:25 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 #ifndef _LOCORE 48 #include <sys/cpu_data.h> 49 #include <sys/device.h> 50 51 #if defined(_KERNEL_OPT) 52 #include "opt_lockdebug.h" 53 #include "opt_multiprocessor.h" 54 #endif 55 56 struct pridtab { 57 int cpu_cid; 58 int cpu_pid; 59 int cpu_rev; /* -1 == wildcard */ 60 int cpu_copts; /* -1 == wildcard */ 61 int cpu_isa; /* -1 == probed (mips32/mips64) */ 62 int cpu_ntlb; /* -1 == unknown, 0 == probed */ 63 int cpu_flags; 64 u_int cpu_cp0flags; /* presence of some cp0 regs */ 65 u_int cpu_cidflags; /* company-specific flags */ 66 const char *cpu_name; 67 }; 68 69 /* 70 * bitfield defines for cpu_cp0flags 71 */ 72 #define MIPS_CP0FL_USE __BIT(0) /* use these flags */ 73 #define MIPS_CP0FL_ECC __BIT(1) 74 #define MIPS_CP0FL_CACHE_ERR __BIT(2) 75 #define MIPS_CP0FL_EIRR __BIT(3) 76 #define MIPS_CP0FL_EIMR __BIT(4) 77 #define MIPS_CP0FL_EBASE __BIT(5) 78 #define MIPS_CP0FL_CONFIG __BIT(6) 79 #define MIPS_CP0FL_CONFIGn(n) (__BIT(7) << ((n) & 7)) 80 81 /* 82 * cpu_cidflags defines, by company 83 */ 84 /* 85 * RMI company-specific cpu_cidflags 86 */ 87 #define MIPS_CIDFL_RMI_TYPE __BITS(2,0) 88 # define CIDFL_RMI_TYPE_XLR 0 89 # define CIDFL_RMI_TYPE_XLS 1 90 # define CIDFL_RMI_TYPE_XLP 2 91 #define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3) 92 # define MIPS_CIDFL_RMI_THREADS_SHIFT 3 93 #define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7) 94 # define MIPS_CIDFL_RMI_CORES_SHIFT 7 95 # define LOG2_1 0 96 # define LOG2_2 1 97 # define LOG2_4 2 98 # define LOG2_8 3 99 # define MIPS_CIDFL_RMI_CPUS(ncores, nthreads) \ 100 ((LOG2_ ## ncores << MIPS_CIDFL_RMI_CORES_SHIFT) \ 101 |(LOG2_ ## nthreads << MIPS_CIDFL_RMI_THREADS_SHIFT)) 102 # define MIPS_CIDFL_RMI_NTHREADS(cidfl) \ 103 (1 << (((cidfl) & MIPS_CIDFL_RMI_THREADS_MASK) \ 104 >> MIPS_CIDFL_RMI_THREADS_SHIFT)) 105 # define MIPS_CIDFL_RMI_NCORES(cidfl) \ 106 (1 << (((cidfl) & MIPS_CIDFL_RMI_CORES_MASK) \ 107 >> MIPS_CIDFL_RMI_CORES_SHIFT)) 108 #define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11) 109 # define MIPS_CIDFL_RMI_L2SZ_SHIFT 11 110 # define RMI_L2SZ_256KB 0 111 # define RMI_L2SZ_512KB 1 112 # define RMI_L2SZ_1MB 2 113 # define RMI_L2SZ_2MB 3 114 # define RMI_L2SZ_4MB 4 115 # define MIPS_CIDFL_RMI_L2(l2sz) \ 116 (RMI_L2SZ_ ## l2sz << MIPS_CIDFL_RMI_L2SZ_SHIFT) 117 # define MIPS_CIDFL_RMI_L2SZ(cidfl) \ 118 ((256*1024) << (((cidfl) & MIPS_CIDFL_RMI_L2SZ_MASK) \ 119 >> MIPS_CIDFL_RMI_L2SZ_SHIFT)) 120 121 122 123 struct cpu_info { 124 struct cpu_data ci_data; /* MI per-cpu data */ 125 struct cpu_info *ci_next; /* Next CPU in list */ 126 cpuid_t ci_cpuid; /* Machine-level identifier */ 127 u_long ci_cpu_freq; /* CPU frequency */ 128 u_long ci_cycles_per_hz; /* CPU freq / hz */ 129 u_long ci_divisor_delay; /* for delay/DELAY */ 130 u_long ci_divisor_recip; /* unused, for obsolete microtime(9) */ 131 struct lwp *ci_curlwp; /* currently running lwp */ 132 struct lwp *ci_fpcurlwp; /* the current FPU owner */ 133 int ci_want_resched; /* user preemption pending */ 134 int ci_mtx_count; /* negative count of held mutexes */ 135 int ci_mtx_oldspl; /* saved SPL value */ 136 int ci_idepth; /* hardware interrupt depth */ 137 device_t ci_dev; /* owning device */ 138 vaddr_t ci_ebase; /* VA of exception base */ 139 paddr_t ci_ebase_pa; /* PA of exception base */ 140 u_long ci_cctr_freq; /* cycle counter frequency */ 141 /* 142 * Per-cpu pmap information 143 */ 144 struct segtab *ci_pmap_segbase; 145 vaddr_t ci_pmap_srcbase; /* starting VA of ephemeral src space */ 146 vaddr_t ci_pmap_dstbase; /* starting VA of ephemeral dst space */ 147 uint32_t ci_pmap_asid_next; /* next asid to be assigned */ 148 uint32_t ci_pmap_asid_generation; /* current asid generation */ 149 uint32_t ci_pmap_asid_reserved; /* base of ASID space */ 150 uint32_t ci_pmap_asid_max; /* max (exclusive) assignable asid */ 151 }; 152 153 #define CPU_INFO_ITERATOR int 154 #define CPU_INFO_FOREACH(cii, ci) \ 155 (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next 156 157 #endif /* !_LOCORE */ 158 #endif /* _KERNEL */ 159 160 /* 161 * CTL_MACHDEP definitions. 162 */ 163 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 164 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 165 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 166 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 167 168 /* 169 * Platform can override, but note this breaks userland compatibility 170 * with other mips platforms. 171 */ 172 #ifndef CPU_MAXID 173 #define CPU_MAXID 5 /* number of valid machdep ids */ 174 175 #endif 176 177 #ifdef _KERNEL 178 #if defined(_LKM) || defined(_STANDALONE) 179 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 180 #define MIPS1 1 181 #define MIPS3 1 182 #define MIPS4 1 183 #define MIPS32 1 184 #define MIPS64 1 185 #endif 186 187 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 188 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 189 #endif 190 191 /* Shortcut for MIPS3 or above defined */ 192 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 193 #define MIPS3_PLUS 1 194 #else 195 #undef MIPS3_PLUS 196 #endif 197 198 /* 199 * Macros to find the CPU architecture we're on at run-time, 200 * or if possible, at compile-time. 201 */ 202 203 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 204 #define CPU_ARCH_MIPS1 (1 << 0) 205 #define CPU_ARCH_MIPS2 (1 << 1) 206 #define CPU_ARCH_MIPS3 (1 << 2) 207 #define CPU_ARCH_MIPS4 (1 << 3) 208 #define CPU_ARCH_MIPS5 (1 << 4) 209 #define CPU_ARCH_MIPS32 (1 << 5) 210 #define CPU_ARCH_MIPS64 (1 << 6) 211 212 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 213 #define MIPS_CURLWP $23 214 #define MIPS_CURLWP_QUOTED "$23" 215 #define MIPS_CURLWP_CARD 23 216 #define MIPS_CURLWP_FRAME(x) FRAME_S7(x) 217 218 #ifndef _LOCORE 219 220 extern struct cpu_info cpu_info_store; 221 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 222 223 #define curlwp mips_curlwp 224 #define curcpu() (curlwp->l_cpu) 225 #define curpcb ((struct pcb *)curlwp->l_addr) 226 #define fpcurlwp (curcpu()->ci_fpcurlwp) 227 #ifdef MULTIPROCESSOR 228 #define cpu_number() (curcpu()->ci_cpuid) 229 #else 230 #define cpu_number() (0) 231 #endif 232 #define cpu_proc_fork(p1, p2) ((void)((p2)->p_md.md_abi = (p1)->p_md.md_abi)) 233 234 /* XXX simonb 235 * Should the following be in a cpu_info type structure? 236 * And how many of these are per-cpu vs. per-system? (Ie, 237 * we can assume that all cpus have the same mmu-type, but 238 * maybe not that all cpus run at the same clock speed. 239 * Some SGI's apparently support R12k and R14k in the same 240 * box.) 241 */ 242 struct mips_options { 243 const struct pridtab *mips_cpu; 244 245 u_int mips_cpu_arch; 246 u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */ 247 u_int mips_cpu_flags; 248 u_int mips_num_tlb_entries; 249 mips_prid_t mips_cpu_id; 250 mips_prid_t mips_fpu_id; 251 bool mips_has_r4k_mmu; 252 bool mips_has_llsc; 253 u_int mips3_pg_shift; 254 u_int mips3_pg_cached; 255 #ifdef MIPS3_PLUS 256 #ifdef _LP64 257 uint64_t mips3_xkphys_cached; 258 #endif 259 uint64_t mips3_tlb_vpn_mask; 260 uint64_t mips3_tlb_pfn_mask; 261 uint32_t mips3_tlb_pg_mask; 262 #endif 263 }; 264 extern struct mips_options mips_options; 265 266 #define CPU_MIPS_R4K_MMU 0x0001 267 #define CPU_MIPS_NO_LLSC 0x0002 268 #define CPU_MIPS_CAUSE_IV 0x0004 269 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 270 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 271 #define CPU_MIPS_CACHED_CCA_SHIFT 4 272 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 273 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 274 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 275 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 276 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 277 #define CPU_MIPS_NO_LLADDR 0x1000 278 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 279 #define MIPS_NOT_SUPP 0x8000 280 281 #endif /* !_LOCORE */ 282 283 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE) 284 285 #if defined(MIPS1) 286 287 # define CPUISMIPS3 0 288 # define CPUIS64BITS 0 289 # define CPUISMIPS32 0 290 # define CPUISMIPS64 0 291 # define CPUISMIPSNN 0 292 # define MIPS_HAS_R4K_MMU 0 293 # define MIPS_HAS_CLOCK 0 294 # define MIPS_HAS_LLSC 0 295 # define MIPS_HAS_LLADDR 0 296 297 #elif defined(MIPS3) || defined(MIPS4) 298 299 # define CPUISMIPS3 1 300 # define CPUIS64BITS 1 301 # define CPUISMIPS32 0 302 # define CPUISMIPS64 0 303 # define CPUISMIPSNN 0 304 # define MIPS_HAS_R4K_MMU 1 305 # define MIPS_HAS_CLOCK 1 306 # if defined(_LOCORE) 307 # if !defined(MIPS3_5900) && !defined(MIPS3_4100) 308 # define MIPS_HAS_LLSC 1 309 # else 310 # define MIPS_HAS_LLSC 0 311 # endif 312 # else /* _LOCORE */ 313 # define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 314 # endif /* _LOCORE */ 315 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 316 317 #elif defined(MIPS32) 318 319 # define CPUISMIPS3 1 320 # define CPUIS64BITS 0 321 # define CPUISMIPS32 1 322 # define CPUISMIPS64 0 323 # define CPUISMIPSNN 1 324 # define MIPS_HAS_R4K_MMU 1 325 # define MIPS_HAS_CLOCK 1 326 # define MIPS_HAS_LLSC 1 327 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 328 329 #elif defined(MIPS64) 330 331 # define CPUISMIPS3 1 332 # define CPUIS64BITS 1 333 # define CPUISMIPS32 0 334 # define CPUISMIPS64 1 335 # define CPUISMIPSNN 1 336 # define MIPS_HAS_R4K_MMU 1 337 # define MIPS_HAS_CLOCK 1 338 # define MIPS_HAS_LLSC 1 339 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 340 341 #endif 342 343 #else /* run-time test */ 344 345 #ifndef _LOCORE 346 347 #define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu) 348 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 349 #define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 350 351 /* This test is ... rather bogus */ 352 #define CPUISMIPS3 ((mips_options.mips_cpu_arch & \ 353 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 354 355 /* And these aren't much better while the previous test exists as is... */ 356 #define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0) 357 #define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0) 358 #define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0) 359 #define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0) 360 #define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 361 #define CPUIS64BITS ((mips_options.mips_cpu_arch & \ 362 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 363 364 #define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) 365 366 #else /* !_LOCORE */ 367 368 #define MIPS_HAS_LLSC 0 369 370 #endif /* !_LOCORE */ 371 372 #endif /* run-time test */ 373 374 #ifndef _LOCORE 375 376 /* 377 * definitions of cpu-dependent requirements 378 * referenced in generic code 379 */ 380 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 381 382 void cpu_intr(uint32_t, uint32_t, vaddr_t, uint32_t); 383 384 /* 385 * Arguments to hardclock and gatherstats encapsulate the previous 386 * machine state in an opaque clockframe. 387 */ 388 struct clockframe { 389 vaddr_t pc; /* program counter at time of interrupt */ 390 uint32_t sr; /* status register at time of interrupt */ 391 u_int ppl; /* previous priority level at time of interrupt */ 392 }; 393 394 /* 395 * A port must provde CLKF_USERMODE() for use in machine-independent code. 396 * These differ on r4000 and r3000 systems; provide them in the 397 * port-dependent file that includes this one, using the macros below. 398 */ 399 400 /* mips1 versions */ 401 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 402 403 /* mips3 versions */ 404 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 405 406 #define CLKF_PC(framep) ((framep)->pc) 407 #define CLKF_INTR(framep) (0) 408 409 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 410 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 411 #endif 412 413 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 414 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 415 #endif 416 417 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 418 #define CLKF_USERMODE(framep) \ 419 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 420 #endif 421 422 /* 423 * This is used during profiling to integrate system time. It can safely 424 * assume that the process is resident. 425 */ 426 #define PROC_PC(p) \ 427 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 428 429 /* 430 * Preempt the current process if in interrupt from user mode, 431 * or after the current trap/syscall if in system mode. 432 */ 433 void cpu_need_resched(struct cpu_info *, int); 434 435 /* 436 * Give a profiling tick to the current process when the user profiling 437 * buffer pages are invalid. On the MIPS, request an ast to send us 438 * through trap, marking the proc as needing a profiling tick. 439 */ 440 #define cpu_need_proftick(l) \ 441 do { \ 442 (l)->l_pflag |= LP_OWEUPC; \ 443 aston(l); \ 444 } while (/*CONSTCOND*/0) 445 446 /* 447 * Notify the current lwp (l) that it has a signal pending, 448 * process as soon as possible. 449 */ 450 #define cpu_signotify(l) aston(l) 451 452 #define aston(l) ((l)->l_md.md_astpending = 1) 453 454 /* 455 * Misc prototypes and variable declarations. 456 */ 457 struct lwp; 458 struct user; 459 460 extern struct segtab *segbase; /* current segtab base */ 461 extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */ 462 463 /* copy.S */ 464 int8_t ufetch_int8(void *); 465 int16_t ufetch_int16(void *); 466 int32_t ufetch_int32(void *); 467 uint8_t ufetch_uint8(void *); 468 uint16_t ufetch_uint16(void *); 469 uint32_t ufetch_uint32(void *); 470 int8_t ufetch_int8_intrsafe(void *); 471 int16_t ufetch_int16_intrsafe(void *); 472 int32_t ufetch_int32_intrsafe(void *); 473 uint8_t ufetch_uint8_intrsafe(void *); 474 uint16_t ufetch_uint16_intrsafe(void *); 475 uint32_t ufetch_uint32_intrsafe(void *); 476 #ifdef _LP64 477 int64_t ufetch_int64(void *); 478 uint64_t ufetch_uint64(void *); 479 int64_t ufetch_int64_intrsafe(void *); 480 uint64_t ufetch_uint64_intrsafe(void *); 481 #endif 482 char ufetch_char(void *); 483 short ufetch_short(void *); 484 int ufetch_int(void *); 485 long ufetch_long(void *); 486 char ufetch_char_intrsafe(void *); 487 short ufetch_short_intrsafe(void *); 488 int ufetch_int_intrsafe(void *); 489 long ufetch_long_intrsafe(void *); 490 491 u_char ufetch_uchar(void *); 492 u_short ufetch_ushort(void *); 493 u_int ufetch_uint(void *); 494 u_long ufetch_ulong(void *); 495 u_char ufetch_uchar_intrsafe(void *); 496 u_short ufetch_ushort_intrsafe(void *); 497 u_int ufetch_uint_intrsafe(void *); 498 u_long ufetch_ulong_intrsafe(void *); 499 void *ufetch_ptr(void *); 500 501 int ustore_int8(void *, int8_t); 502 int ustore_int16(void *, int16_t); 503 int ustore_int32(void *, int32_t); 504 int ustore_uint8(void *, uint8_t); 505 int ustore_uint16(void *, uint16_t); 506 int ustore_uint32(void *, uint32_t); 507 int ustore_int8_intrsafe(void *, int8_t); 508 int ustore_int16_intrsafe(void *, int16_t); 509 int ustore_int32_intrsafe(void *, int32_t); 510 int ustore_uint8_intrsafe(void *, uint8_t); 511 int ustore_uint16_intrsafe(void *, uint16_t); 512 int ustore_uint32_intrsafe(void *, uint32_t); 513 #ifdef _LP64 514 int ustore_int64(void *, int64_t); 515 int ustore_uint64(void *, uint64_t); 516 int ustore_int64_intrsafe(void *, int64_t); 517 int ustore_uint64_intrsafe(void *, uint64_t); 518 #endif 519 int ustore_char(void *, char); 520 int ustore_char_intrsafe(void *, char); 521 int ustore_short(void *, short); 522 int ustore_short_intrsafe(void *, short); 523 int ustore_int(void *, int); 524 int ustore_int_intrsafe(void *, int); 525 int ustore_long(void *, long); 526 int ustore_long_intrsafe(void *, long); 527 int ustore_uchar(void *, u_char); 528 int ustore_uchar_intrsafe(void *, u_char); 529 int ustore_ushort(void *, u_short); 530 int ustore_ushort_intrsafe(void *, u_short); 531 int ustore_uint(void *, u_int); 532 int ustore_uint_intrsafe(void *, u_int); 533 int ustore_ulong(void *, u_long); 534 int ustore_ulong_intrsafe(void *, u_long); 535 int ustore_ptr(void *, void *); 536 int ustore_ptr_intrsafe(void *, void *); 537 538 int ustore_uint32_isync(void *, uint32_t); 539 540 /* trap.c */ 541 void netintr(void); 542 int kdbpeek(vaddr_t); 543 544 /* mips_machdep.c */ 545 struct mips_vmfreelist; 546 struct phys_ram_seg; 547 void dumpsys(void); 548 int savectx(struct user *); 549 void mips_vector_init(void); 550 void mips_init_msgbuf(void); 551 void mips_init_lwp0_uarea(void); 552 void mips_page_physload(vaddr_t, vaddr_t, 553 const struct phys_ram_seg *, size_t, 554 const struct mips_vmfreelist *, size_t); 555 void savefpregs(struct lwp *); 556 void loadfpregs(struct lwp *); 557 void cpu_identify(device_t); 558 #ifdef MULTIPROCESSOR 559 void cpu_boot_secondary_processors(void); 560 #endif 561 562 /* locore*.S */ 563 int badaddr(void *, size_t); 564 int badaddr64(uint64_t, size_t); 565 566 #endif /* ! _LOCORE */ 567 #endif /* _KERNEL */ 568 #endif /* _CPU_H_ */ 569
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