cpu.h revision 1.90.16.18
1 /* $NetBSD: cpu.h,v 1.90.16.18 2010/02/05 07:36:51 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 #ifndef _LOCORE 48 #include <sys/cpu_data.h> 49 #include <sys/device.h> 50 51 #if defined(_KERNEL_OPT) 52 #include "opt_lockdebug.h" 53 #include "opt_multiprocessor.h" 54 #endif 55 56 struct pridtab { 57 int cpu_cid; 58 int cpu_pid; 59 int cpu_rev; /* -1 == wildcard */ 60 int cpu_copts; /* -1 == wildcard */ 61 int cpu_isa; /* -1 == probed (mips32/mips64) */ 62 int cpu_ntlb; /* -1 == unknown, 0 == probed */ 63 int cpu_flags; 64 u_int cpu_cp0flags; /* presence of some cp0 regs */ 65 u_int cpu_cidflags; /* company-specific flags */ 66 const char *cpu_name; 67 }; 68 69 /* 70 * bitfield defines for cpu_cp0flags 71 */ 72 #define MIPS_CP0FL_USE __BIT(0) /* use these flags */ 73 #define MIPS_CP0FL_ECC __BIT(1) 74 #define MIPS_CP0FL_CACHE_ERR __BIT(2) 75 #define MIPS_CP0FL_EIRR __BIT(3) 76 #define MIPS_CP0FL_EIMR __BIT(4) 77 #define MIPS_CP0FL_EBASE __BIT(5) 78 #define MIPS_CP0FL_CONFIG __BIT(6) 79 #define MIPS_CP0FL_CONFIGn(n) (__BIT(7) << ((n) & 7)) 80 81 /* 82 * cpu_cidflags defines, by company 83 */ 84 /* 85 * RMI company-specific cpu_cidflags 86 */ 87 #define MIPS_CIDFL_RMI_TYPE __BITS(2,0) 88 # define CIDFL_RMI_TYPE_XLR 0 89 # define CIDFL_RMI_TYPE_XLS 1 90 # define CIDFL_RMI_TYPE_XLP 2 91 #define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3) 92 # define MIPS_CIDFL_RMI_THREADS_SHIFT 3 93 #define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7) 94 # define MIPS_CIDFL_RMI_CORES_SHIFT 7 95 # define LOG2_1 0 96 # define LOG2_2 1 97 # define LOG2_4 2 98 # define LOG2_8 3 99 # define MIPS_CIDFL_RMI_CPUS(ncores, nthreads) \ 100 ((LOG2_ ## ncores << MIPS_CIDFL_RMI_CORES_SHIFT) \ 101 |(LOG2_ ## nthreads << MIPS_CIDFL_RMI_THREADS_SHIFT)) 102 # define MIPS_CIDFL_RMI_NTHREADS(cidfl) \ 103 (1 << (((cidfl) & MIPS_CIDFL_RMI_THREADS_MASK) \ 104 >> MIPS_CIDFL_RMI_THREADS_SHIFT)) 105 # define MIPS_CIDFL_RMI_NCORES(cidfl) \ 106 (1 << (((cidfl) & MIPS_CIDFL_RMI_CORES_MASK) \ 107 >> MIPS_CIDFL_RMI_CORES_SHIFT)) 108 #define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11) 109 # define MIPS_CIDFL_RMI_L2SZ_SHIFT 11 110 # define RMI_L2SZ_256KB 0 111 # define RMI_L2SZ_512KB 1 112 # define RMI_L2SZ_1MB 2 113 # define RMI_L2SZ_2MB 3 114 # define RMI_L2SZ_4MB 4 115 # define MIPS_CIDFL_RMI_L2(l2sz) \ 116 (RMI_L2SZ_ ## l2sz << MIPS_CIDFL_RMI_L2SZ_SHIFT) 117 # define MIPS_CIDFL_RMI_L2SZ(cidfl) \ 118 ((256*1024) << (((cidfl) & MIPS_CIDFL_RMI_L2SZ_MASK) \ 119 >> MIPS_CIDFL_RMI_L2SZ_SHIFT)) 120 121 122 123 struct cpu_info { 124 struct cpu_data ci_data; /* MI per-cpu data */ 125 struct cpu_info *ci_next; /* Next CPU in list */ 126 cpuid_t ci_cpuid; /* Machine-level identifier */ 127 u_long ci_cpu_freq; /* CPU frequency */ 128 u_long ci_cycles_per_hz; /* CPU freq / hz */ 129 u_long ci_divisor_delay; /* for delay/DELAY */ 130 u_long ci_divisor_recip; /* unused, for obsolete microtime(9) */ 131 struct lwp *ci_curlwp; /* currently running lwp */ 132 struct lwp *ci_fpcurlwp; /* the current FPU owner */ 133 int ci_want_resched; /* user preemption pending */ 134 int ci_mtx_count; /* negative count of held mutexes */ 135 int ci_mtx_oldspl; /* saved SPL value */ 136 int ci_idepth; /* hardware interrupt depth */ 137 device_t ci_dev; /* owning device */ 138 vaddr_t ci_ebase; /* VA of exception base */ 139 paddr_t ci_ebase_pa; /* PA of exception base */ 140 u_long ci_cctr_freq; /* cycle counter frequency */ 141 struct lwp *ci_softlwps[SOFTINT_COUNT]; 142 #define ci_softints ci_data.cpu_softints 143 /* 144 * Per-cpu pmap information 145 */ 146 struct segtab *ci_pmap_segbase; 147 vaddr_t ci_pmap_srcbase; /* starting VA of ephemeral src space */ 148 vaddr_t ci_pmap_dstbase; /* starting VA of ephemeral dst space */ 149 uint32_t ci_pmap_asid_next; /* next asid to be assigned */ 150 uint32_t ci_pmap_asid_generation; /* current asid generation */ 151 uint32_t ci_pmap_asid_reserved; /* base of ASID space */ 152 uint32_t ci_pmap_asid_max; /* max (exclusive) assignable asid */ 153 }; 154 155 #define CPU_INFO_ITERATOR int 156 #define CPU_INFO_FOREACH(cii, ci) \ 157 (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next 158 159 #endif /* !_LOCORE */ 160 #endif /* _KERNEL */ 161 162 /* 163 * CTL_MACHDEP definitions. 164 */ 165 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 166 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 167 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 168 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 169 170 /* 171 * Platform can override, but note this breaks userland compatibility 172 * with other mips platforms. 173 */ 174 #ifndef CPU_MAXID 175 #define CPU_MAXID 5 /* number of valid machdep ids */ 176 177 #endif 178 179 #ifdef _KERNEL 180 #if defined(_LKM) || defined(_STANDALONE) 181 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 182 #define MIPS1 1 183 #define MIPS3 1 184 #define MIPS4 1 185 #define MIPS32 1 186 #define MIPS64 1 187 #endif 188 189 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 190 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 191 #endif 192 193 /* Shortcut for MIPS3 or above defined */ 194 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 195 #define MIPS3_PLUS 1 196 #else 197 #undef MIPS3_PLUS 198 #endif 199 200 /* 201 * Macros to find the CPU architecture we're on at run-time, 202 * or if possible, at compile-time. 203 */ 204 205 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 206 #define CPU_ARCH_MIPS1 (1 << 0) 207 #define CPU_ARCH_MIPS2 (1 << 1) 208 #define CPU_ARCH_MIPS3 (1 << 2) 209 #define CPU_ARCH_MIPS4 (1 << 3) 210 #define CPU_ARCH_MIPS5 (1 << 4) 211 #define CPU_ARCH_MIPS32 (1 << 5) 212 #define CPU_ARCH_MIPS64 (1 << 6) 213 214 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 215 #define MIPS_CURLWP $24 216 #define MIPS_CURLWP_QUOTED "$24" 217 #define MIPS_CURLWP_LABEL _L_T8 218 #define TF_MIPS_CURLWP(x) TF_REG_T8(x) 219 220 #ifndef _LOCORE 221 222 extern struct cpu_info cpu_info_store; 223 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 224 225 #define curlwp mips_curlwp 226 #define curcpu() (curlwp->l_cpu) 227 #define curpcb ((struct pcb *)curlwp->l_addr) 228 #define fpcurlwp (curcpu()->ci_fpcurlwp) 229 #ifdef MULTIPROCESSOR 230 #define cpu_number() (curcpu()->ci_cpuid) 231 #else 232 #define cpu_number() (0) 233 #endif 234 #define cpu_proc_fork(p1, p2) ((void)((p2)->p_md.md_abi = (p1)->p_md.md_abi)) 235 236 /* XXX simonb 237 * Should the following be in a cpu_info type structure? 238 * And how many of these are per-cpu vs. per-system? (Ie, 239 * we can assume that all cpus have the same mmu-type, but 240 * maybe not that all cpus run at the same clock speed. 241 * Some SGI's apparently support R12k and R14k in the same 242 * box.) 243 */ 244 struct mips_options { 245 const struct pridtab *mips_cpu; 246 247 u_int mips_cpu_arch; 248 u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */ 249 u_int mips_cpu_flags; 250 u_int mips_num_tlb_entries; 251 mips_prid_t mips_cpu_id; 252 mips_prid_t mips_fpu_id; 253 bool mips_has_r4k_mmu; 254 bool mips_has_llsc; 255 u_int mips3_pg_shift; 256 u_int mips3_pg_cached; 257 #ifdef MIPS3_PLUS 258 #ifdef _LP64 259 uint64_t mips3_xkphys_cached; 260 #endif 261 uint64_t mips3_tlb_vpn_mask; 262 uint64_t mips3_tlb_pfn_mask; 263 uint32_t mips3_tlb_pg_mask; 264 #endif 265 }; 266 extern struct mips_options mips_options; 267 268 #define CPU_MIPS_R4K_MMU 0x0001 269 #define CPU_MIPS_NO_LLSC 0x0002 270 #define CPU_MIPS_CAUSE_IV 0x0004 271 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 272 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 273 #define CPU_MIPS_CACHED_CCA_SHIFT 4 274 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 275 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 276 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 277 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 278 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 279 #define CPU_MIPS_NO_LLADDR 0x1000 280 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 281 #define MIPS_NOT_SUPP 0x8000 282 283 #endif /* !_LOCORE */ 284 285 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE) 286 287 #if defined(MIPS1) 288 289 # define CPUISMIPS3 0 290 # define CPUIS64BITS 0 291 # define CPUISMIPS32 0 292 # define CPUISMIPS64 0 293 # define CPUISMIPSNN 0 294 # define MIPS_HAS_R4K_MMU 0 295 # define MIPS_HAS_CLOCK 0 296 # define MIPS_HAS_LLSC 0 297 # define MIPS_HAS_LLADDR 0 298 299 #elif defined(MIPS3) || defined(MIPS4) 300 301 # define CPUISMIPS3 1 302 # define CPUIS64BITS 1 303 # define CPUISMIPS32 0 304 # define CPUISMIPS64 0 305 # define CPUISMIPSNN 0 306 # define MIPS_HAS_R4K_MMU 1 307 # define MIPS_HAS_CLOCK 1 308 # if defined(_LOCORE) 309 # if !defined(MIPS3_5900) && !defined(MIPS3_4100) 310 # define MIPS_HAS_LLSC 1 311 # else 312 # define MIPS_HAS_LLSC 0 313 # endif 314 # else /* _LOCORE */ 315 # define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 316 # endif /* _LOCORE */ 317 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 318 319 #elif defined(MIPS32) 320 321 # define CPUISMIPS3 1 322 # define CPUIS64BITS 0 323 # define CPUISMIPS32 1 324 # define CPUISMIPS64 0 325 # define CPUISMIPSNN 1 326 # define MIPS_HAS_R4K_MMU 1 327 # define MIPS_HAS_CLOCK 1 328 # define MIPS_HAS_LLSC 1 329 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 330 331 #elif defined(MIPS64) 332 333 # define CPUISMIPS3 1 334 # define CPUIS64BITS 1 335 # define CPUISMIPS32 0 336 # define CPUISMIPS64 1 337 # define CPUISMIPSNN 1 338 # define MIPS_HAS_R4K_MMU 1 339 # define MIPS_HAS_CLOCK 1 340 # define MIPS_HAS_LLSC 1 341 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 342 343 #endif 344 345 #else /* run-time test */ 346 347 #ifndef _LOCORE 348 349 #define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu) 350 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 351 #define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 352 353 /* This test is ... rather bogus */ 354 #define CPUISMIPS3 ((mips_options.mips_cpu_arch & \ 355 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 356 357 /* And these aren't much better while the previous test exists as is... */ 358 #define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0) 359 #define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0) 360 #define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0) 361 #define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0) 362 #define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 363 #define CPUIS64BITS ((mips_options.mips_cpu_arch & \ 364 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 365 366 #define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) 367 368 #else /* !_LOCORE */ 369 370 #define MIPS_HAS_LLSC 0 371 372 #endif /* !_LOCORE */ 373 374 #endif /* run-time test */ 375 376 #ifndef _LOCORE 377 378 /* 379 * definitions of cpu-dependent requirements 380 * referenced in generic code 381 */ 382 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 383 384 void cpu_intr(uint32_t, uint32_t, vaddr_t, uint32_t); 385 386 /* 387 * Arguments to hardclock and gatherstats encapsulate the previous 388 * machine state in an opaque clockframe. 389 */ 390 struct clockframe { 391 vaddr_t pc; /* program counter at time of interrupt */ 392 uint32_t sr; /* status register at time of interrupt */ 393 u_int ppl; /* previous priority level at time of interrupt */ 394 }; 395 396 /* 397 * A port must provde CLKF_USERMODE() for use in machine-independent code. 398 * These differ on r4000 and r3000 systems; provide them in the 399 * port-dependent file that includes this one, using the macros below. 400 */ 401 402 /* mips1 versions */ 403 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 404 405 /* mips3 versions */ 406 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 407 408 #define CLKF_PC(framep) ((framep)->pc) 409 #define CLKF_INTR(framep) (0) 410 411 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 412 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 413 #endif 414 415 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 416 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 417 #endif 418 419 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 420 #define CLKF_USERMODE(framep) \ 421 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 422 #endif 423 424 /* 425 * This is used during profiling to integrate system time. It can safely 426 * assume that the process is resident. 427 */ 428 #define PROC_PC(p) \ 429 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 430 431 /* 432 * Preempt the current process if in interrupt from user mode, 433 * or after the current trap/syscall if in system mode. 434 */ 435 void cpu_need_resched(struct cpu_info *, int); 436 437 /* 438 * Give a profiling tick to the current process when the user profiling 439 * buffer pages are invalid. On the MIPS, request an ast to send us 440 * through trap, marking the proc as needing a profiling tick. 441 */ 442 #define cpu_need_proftick(l) \ 443 do { \ 444 (l)->l_pflag |= LP_OWEUPC; \ 445 aston(l); \ 446 } while (/*CONSTCOND*/0) 447 448 /* 449 * Notify the current lwp (l) that it has a signal pending, 450 * process as soon as possible. 451 */ 452 #define cpu_signotify(l) aston(l) 453 454 #define aston(l) ((l)->l_md.md_astpending = 1) 455 456 /* 457 * Misc prototypes and variable declarations. 458 */ 459 struct lwp; 460 struct user; 461 462 extern struct segtab *segbase; /* current segtab base */ 463 extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */ 464 465 /* copy.S */ 466 int8_t ufetch_int8(void *); 467 int16_t ufetch_int16(void *); 468 int32_t ufetch_int32(void *); 469 uint8_t ufetch_uint8(void *); 470 uint16_t ufetch_uint16(void *); 471 uint32_t ufetch_uint32(void *); 472 int8_t ufetch_int8_intrsafe(void *); 473 int16_t ufetch_int16_intrsafe(void *); 474 int32_t ufetch_int32_intrsafe(void *); 475 uint8_t ufetch_uint8_intrsafe(void *); 476 uint16_t ufetch_uint16_intrsafe(void *); 477 uint32_t ufetch_uint32_intrsafe(void *); 478 #ifdef _LP64 479 int64_t ufetch_int64(void *); 480 uint64_t ufetch_uint64(void *); 481 int64_t ufetch_int64_intrsafe(void *); 482 uint64_t ufetch_uint64_intrsafe(void *); 483 #endif 484 char ufetch_char(void *); 485 short ufetch_short(void *); 486 int ufetch_int(void *); 487 long ufetch_long(void *); 488 char ufetch_char_intrsafe(void *); 489 short ufetch_short_intrsafe(void *); 490 int ufetch_int_intrsafe(void *); 491 long ufetch_long_intrsafe(void *); 492 493 u_char ufetch_uchar(void *); 494 u_short ufetch_ushort(void *); 495 u_int ufetch_uint(void *); 496 u_long ufetch_ulong(void *); 497 u_char ufetch_uchar_intrsafe(void *); 498 u_short ufetch_ushort_intrsafe(void *); 499 u_int ufetch_uint_intrsafe(void *); 500 u_long ufetch_ulong_intrsafe(void *); 501 void *ufetch_ptr(void *); 502 503 int ustore_int8(void *, int8_t); 504 int ustore_int16(void *, int16_t); 505 int ustore_int32(void *, int32_t); 506 int ustore_uint8(void *, uint8_t); 507 int ustore_uint16(void *, uint16_t); 508 int ustore_uint32(void *, uint32_t); 509 int ustore_int8_intrsafe(void *, int8_t); 510 int ustore_int16_intrsafe(void *, int16_t); 511 int ustore_int32_intrsafe(void *, int32_t); 512 int ustore_uint8_intrsafe(void *, uint8_t); 513 int ustore_uint16_intrsafe(void *, uint16_t); 514 int ustore_uint32_intrsafe(void *, uint32_t); 515 #ifdef _LP64 516 int ustore_int64(void *, int64_t); 517 int ustore_uint64(void *, uint64_t); 518 int ustore_int64_intrsafe(void *, int64_t); 519 int ustore_uint64_intrsafe(void *, uint64_t); 520 #endif 521 int ustore_char(void *, char); 522 int ustore_char_intrsafe(void *, char); 523 int ustore_short(void *, short); 524 int ustore_short_intrsafe(void *, short); 525 int ustore_int(void *, int); 526 int ustore_int_intrsafe(void *, int); 527 int ustore_long(void *, long); 528 int ustore_long_intrsafe(void *, long); 529 int ustore_uchar(void *, u_char); 530 int ustore_uchar_intrsafe(void *, u_char); 531 int ustore_ushort(void *, u_short); 532 int ustore_ushort_intrsafe(void *, u_short); 533 int ustore_uint(void *, u_int); 534 int ustore_uint_intrsafe(void *, u_int); 535 int ustore_ulong(void *, u_long); 536 int ustore_ulong_intrsafe(void *, u_long); 537 int ustore_ptr(void *, void *); 538 int ustore_ptr_intrsafe(void *, void *); 539 540 int ustore_uint32_isync(void *, uint32_t); 541 542 /* trap.c */ 543 void netintr(void); 544 int kdbpeek(vaddr_t); 545 546 /* mips_machdep.c */ 547 struct mips_vmfreelist; 548 struct phys_ram_seg; 549 void dumpsys(void); 550 int savectx(struct user *); 551 void mips_vector_init(void); 552 void mips_init_msgbuf(void); 553 void mips_init_lwp0_uarea(void); 554 void mips_page_physload(vaddr_t, vaddr_t, 555 const struct phys_ram_seg *, size_t, 556 const struct mips_vmfreelist *, size_t); 557 void savefpregs(struct lwp *); 558 void loadfpregs(struct lwp *); 559 void cpu_identify(device_t); 560 #ifdef MULTIPROCESSOR 561 void cpu_boot_secondary_processors(void); 562 #endif 563 564 /* locore*.S */ 565 int badaddr(void *, size_t); 566 int badaddr64(uint64_t, size_t); 567 568 /* vm_machdep.c */ 569 void cpu_uarea_remap(struct lwp *); 570 571 #endif /* ! _LOCORE */ 572 #endif /* _KERNEL */ 573 #endif /* _CPU_H_ */ 574
Indexes created Mon Oct 13 01:09:56 GMT 2025