cpu.h revision 1.90.16.19
1 /* $NetBSD: cpu.h,v 1.90.16.19 2010/02/15 07:36:03 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 48 #ifndef _LOCORE 49 #include <sys/cpu_data.h> 50 #include <sys/device.h> 51 52 #if defined(_KERNEL_OPT) 53 #include "opt_lockdebug.h" 54 #include "opt_multiprocessor.h" 55 #endif 56 57 struct pridtab { 58 int cpu_cid; 59 int cpu_pid; 60 int cpu_rev; /* -1 == wildcard */ 61 int cpu_copts; /* -1 == wildcard */ 62 int cpu_isa; /* -1 == probed (mips32/mips64) */ 63 int cpu_ntlb; /* -1 == unknown, 0 == probed */ 64 int cpu_flags; 65 u_int cpu_cp0flags; /* presence of some cp0 regs */ 66 u_int cpu_cidflags; /* company-specific flags */ 67 const char *cpu_name; 68 }; 69 70 /* 71 * bitfield defines for cpu_cp0flags 72 */ 73 #define MIPS_CP0FL_USE __BIT(0) /* use these flags */ 74 #define MIPS_CP0FL_ECC __BIT(1) 75 #define MIPS_CP0FL_CACHE_ERR __BIT(2) 76 #define MIPS_CP0FL_EIRR __BIT(3) 77 #define MIPS_CP0FL_EIMR __BIT(4) 78 #define MIPS_CP0FL_EBASE __BIT(5) 79 #define MIPS_CP0FL_CONFIG __BIT(6) 80 #define MIPS_CP0FL_CONFIGn(n) (__BIT(7) << ((n) & 7)) 81 82 /* 83 * cpu_cidflags defines, by company 84 */ 85 /* 86 * RMI company-specific cpu_cidflags 87 */ 88 #define MIPS_CIDFL_RMI_TYPE __BITS(2,0) 89 # define CIDFL_RMI_TYPE_XLR 0 90 # define CIDFL_RMI_TYPE_XLS 1 91 # define CIDFL_RMI_TYPE_XLP 2 92 #define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3) 93 # define MIPS_CIDFL_RMI_THREADS_SHIFT 3 94 #define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7) 95 # define MIPS_CIDFL_RMI_CORES_SHIFT 7 96 # define LOG2_1 0 97 # define LOG2_2 1 98 # define LOG2_4 2 99 # define LOG2_8 3 100 # define MIPS_CIDFL_RMI_CPUS(ncores, nthreads) \ 101 ((LOG2_ ## ncores << MIPS_CIDFL_RMI_CORES_SHIFT) \ 102 |(LOG2_ ## nthreads << MIPS_CIDFL_RMI_THREADS_SHIFT)) 103 # define MIPS_CIDFL_RMI_NTHREADS(cidfl) \ 104 (1 << (((cidfl) & MIPS_CIDFL_RMI_THREADS_MASK) \ 105 >> MIPS_CIDFL_RMI_THREADS_SHIFT)) 106 # define MIPS_CIDFL_RMI_NCORES(cidfl) \ 107 (1 << (((cidfl) & MIPS_CIDFL_RMI_CORES_MASK) \ 108 >> MIPS_CIDFL_RMI_CORES_SHIFT)) 109 #define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11) 110 # define MIPS_CIDFL_RMI_L2SZ_SHIFT 11 111 # define RMI_L2SZ_256KB 0 112 # define RMI_L2SZ_512KB 1 113 # define RMI_L2SZ_1MB 2 114 # define RMI_L2SZ_2MB 3 115 # define RMI_L2SZ_4MB 4 116 # define MIPS_CIDFL_RMI_L2(l2sz) \ 117 (RMI_L2SZ_ ## l2sz << MIPS_CIDFL_RMI_L2SZ_SHIFT) 118 # define MIPS_CIDFL_RMI_L2SZ(cidfl) \ 119 ((256*1024) << (((cidfl) & MIPS_CIDFL_RMI_L2SZ_MASK) \ 120 >> MIPS_CIDFL_RMI_L2SZ_SHIFT)) 121 122 123 124 struct cpu_info { 125 struct cpu_data ci_data; /* MI per-cpu data */ 126 struct cpu_info *ci_next; /* Next CPU in list */ 127 cpuid_t ci_cpuid; /* Machine-level identifier */ 128 u_long ci_cpu_freq; /* CPU frequency */ 129 u_long ci_cycles_per_hz; /* CPU freq / hz */ 130 u_long ci_divisor_delay; /* for delay/DELAY */ 131 u_long ci_divisor_recip; /* unused, for obsolete microtime(9) */ 132 struct lwp *ci_curlwp; /* currently running lwp */ 133 struct lwp *ci_fpcurlwp; /* the current FPU owner */ 134 int ci_want_resched; /* user preemption pending */ 135 int ci_mtx_count; /* negative count of held mutexes */ 136 int ci_mtx_oldspl; /* saved SPL value */ 137 int ci_idepth; /* hardware interrupt depth */ 138 int ci_cpl; /* current [interrupt] priority level */ 139 device_t ci_dev; /* owning device */ 140 vaddr_t ci_ebase; /* VA of exception base */ 141 paddr_t ci_ebase_pa; /* PA of exception base */ 142 u_long ci_cctr_freq; /* cycle counter frequency */ 143 struct lwp *ci_softlwps[SOFTINT_COUNT]; 144 #define ci_softints ci_data.cpu_softints 145 /* 146 * Per-cpu pmap information 147 */ 148 struct segtab *ci_pmap_segbase; 149 vaddr_t ci_pmap_srcbase; /* starting VA of ephemeral src space */ 150 vaddr_t ci_pmap_dstbase; /* starting VA of ephemeral dst space */ 151 uint32_t ci_pmap_asid_next; /* next asid to be assigned */ 152 uint32_t ci_pmap_asid_generation; /* current asid generation */ 153 uint32_t ci_pmap_asid_reserved; /* base of ASID space */ 154 uint32_t ci_pmap_asid_max; /* max (exclusive) assignable asid */ 155 }; 156 157 #define CPU_INFO_ITERATOR int 158 #define CPU_INFO_FOREACH(cii, ci) \ 159 (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next 160 161 #endif /* !_LOCORE */ 162 #endif /* _KERNEL */ 163 164 /* 165 * CTL_MACHDEP definitions. 166 */ 167 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 168 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 169 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 170 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 171 172 /* 173 * Platform can override, but note this breaks userland compatibility 174 * with other mips platforms. 175 */ 176 #ifndef CPU_MAXID 177 #define CPU_MAXID 5 /* number of valid machdep ids */ 178 179 #endif 180 181 #ifdef _KERNEL 182 #if defined(_LKM) || defined(_STANDALONE) 183 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 184 #define MIPS1 1 185 #define MIPS3 1 186 #define MIPS4 1 187 #define MIPS32 1 188 #define MIPS64 1 189 #endif 190 191 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 192 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 193 #endif 194 195 /* Shortcut for MIPS3 or above defined */ 196 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 197 #define MIPS3_PLUS 1 198 #else 199 #undef MIPS3_PLUS 200 #endif 201 202 /* 203 * Macros to find the CPU architecture we're on at run-time, 204 * or if possible, at compile-time. 205 */ 206 207 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 208 #define CPU_ARCH_MIPS1 (1 << 0) 209 #define CPU_ARCH_MIPS2 (1 << 1) 210 #define CPU_ARCH_MIPS3 (1 << 2) 211 #define CPU_ARCH_MIPS4 (1 << 3) 212 #define CPU_ARCH_MIPS5 (1 << 4) 213 #define CPU_ARCH_MIPS32 (1 << 5) 214 #define CPU_ARCH_MIPS64 (1 << 6) 215 216 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 217 #define MIPS_CURLWP $24 218 #define MIPS_CURLWP_QUOTED "$24" 219 #define MIPS_CURLWP_LABEL _L_T8 220 #define TF_MIPS_CURLWP(x) TF_REG_T8(x) 221 222 #ifndef _LOCORE 223 224 extern struct cpu_info cpu_info_store; 225 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 226 227 #define curlwp mips_curlwp 228 #define curcpu() (curlwp->l_cpu) 229 #define curpcb (&curlwp->l_addr->u_pcb) 230 #define fpcurlwp (curcpu()->ci_fpcurlwp) 231 #ifdef MULTIPROCESSOR 232 #define cpu_number() (curcpu()->ci_cpuid) 233 #else 234 #define cpu_number() (0) 235 #endif 236 #define cpu_proc_fork(p1, p2) ((void)((p2)->p_md.md_abi = (p1)->p_md.md_abi)) 237 238 #include <mips/locore.h> 239 240 /* XXX simonb 241 * Should the following be in a cpu_info type structure? 242 * And how many of these are per-cpu vs. per-system? (Ie, 243 * we can assume that all cpus have the same mmu-type, but 244 * maybe not that all cpus run at the same clock speed. 245 * Some SGI's apparently support R12k and R14k in the same 246 * box.) 247 */ 248 struct mips_options { 249 const struct pridtab *mips_cpu; 250 251 u_int mips_cpu_arch; 252 u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */ 253 u_int mips_cpu_flags; 254 u_int mips_num_tlb_entries; 255 mips_prid_t mips_cpu_id; 256 mips_prid_t mips_fpu_id; 257 bool mips_has_r4k_mmu; 258 bool mips_has_llsc; 259 u_int mips3_pg_shift; 260 u_int mips3_pg_cached; 261 #ifdef MIPS3_PLUS 262 #ifdef _LP64 263 uint64_t mips3_xkphys_cached; 264 #endif 265 uint64_t mips3_tlb_vpn_mask; 266 uint64_t mips3_tlb_pfn_mask; 267 uint32_t mips3_tlb_pg_mask; 268 #endif 269 }; 270 extern struct mips_options mips_options; 271 272 #define CPU_MIPS_R4K_MMU 0x0001 273 #define CPU_MIPS_NO_LLSC 0x0002 274 #define CPU_MIPS_CAUSE_IV 0x0004 275 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 276 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 277 #define CPU_MIPS_CACHED_CCA_SHIFT 4 278 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 279 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 280 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 281 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 282 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 283 #define CPU_MIPS_NO_LLADDR 0x1000 284 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 285 #define MIPS_NOT_SUPP 0x8000 286 287 #endif /* !_LOCORE */ 288 289 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE) 290 291 #if defined(MIPS1) 292 293 # define CPUISMIPS3 0 294 # define CPUIS64BITS 0 295 # define CPUISMIPS32 0 296 # define CPUISMIPS64 0 297 # define CPUISMIPSNN 0 298 # define MIPS_HAS_R4K_MMU 0 299 # define MIPS_HAS_CLOCK 0 300 # define MIPS_HAS_LLSC 0 301 # define MIPS_HAS_LLADDR 0 302 303 #elif defined(MIPS3) || defined(MIPS4) 304 305 # define CPUISMIPS3 1 306 # define CPUIS64BITS 1 307 # define CPUISMIPS32 0 308 # define CPUISMIPS64 0 309 # define CPUISMIPSNN 0 310 # define MIPS_HAS_R4K_MMU 1 311 # define MIPS_HAS_CLOCK 1 312 # if defined(_LOCORE) 313 # if !defined(MIPS3_5900) && !defined(MIPS3_4100) 314 # define MIPS_HAS_LLSC 1 315 # else 316 # define MIPS_HAS_LLSC 0 317 # endif 318 # else /* _LOCORE */ 319 # define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 320 # endif /* _LOCORE */ 321 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 322 323 #elif defined(MIPS32) 324 325 # define CPUISMIPS3 1 326 # define CPUIS64BITS 0 327 # define CPUISMIPS32 1 328 # define CPUISMIPS64 0 329 # define CPUISMIPSNN 1 330 # define MIPS_HAS_R4K_MMU 1 331 # define MIPS_HAS_CLOCK 1 332 # define MIPS_HAS_LLSC 1 333 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 334 335 #elif defined(MIPS64) 336 337 # define CPUISMIPS3 1 338 # define CPUIS64BITS 1 339 # define CPUISMIPS32 0 340 # define CPUISMIPS64 1 341 # define CPUISMIPSNN 1 342 # define MIPS_HAS_R4K_MMU 1 343 # define MIPS_HAS_CLOCK 1 344 # define MIPS_HAS_LLSC 1 345 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 346 347 #endif 348 349 #else /* run-time test */ 350 351 #ifndef _LOCORE 352 353 #define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu) 354 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 355 #define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 356 357 /* This test is ... rather bogus */ 358 #define CPUISMIPS3 ((mips_options.mips_cpu_arch & \ 359 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 360 361 /* And these aren't much better while the previous test exists as is... */ 362 #define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0) 363 #define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0) 364 #define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0) 365 #define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0) 366 #define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 367 #define CPUIS64BITS ((mips_options.mips_cpu_arch & \ 368 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 369 370 #define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) 371 372 #else /* !_LOCORE */ 373 374 #define MIPS_HAS_LLSC 0 375 376 #endif /* !_LOCORE */ 377 378 #endif /* run-time test */ 379 380 #ifndef _LOCORE 381 382 /* 383 * definitions of cpu-dependent requirements 384 * referenced in generic code 385 */ 386 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 387 388 /* 389 * cpu_intr(ppl, pc, status); (most state needed by clockframe) 390 */ 391 void cpu_intr(int, vaddr_t, uint32_t); 392 393 /* 394 * Arguments to hardclock and gatherstats encapsulate the previous 395 * machine state in an opaque clockframe. 396 */ 397 struct clockframe { 398 vaddr_t pc; /* program counter at time of interrupt */ 399 uint32_t sr; /* status register at time of interrupt */ 400 bool intr; /* interrupted a interrupt */ 401 }; 402 403 /* 404 * A port must provde CLKF_USERMODE() for use in machine-independent code. 405 * These differ on r4000 and r3000 systems; provide them in the 406 * port-dependent file that includes this one, using the macros below. 407 */ 408 409 /* mips1 versions */ 410 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 411 412 /* mips3 versions */ 413 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 414 415 #define CLKF_PC(framep) ((framep)->pc) 416 #define CLKF_INTR(framep) ((framep)->intr) 417 418 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 419 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 420 #endif 421 422 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 423 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 424 #endif 425 426 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 427 #define CLKF_USERMODE(framep) \ 428 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 429 #endif 430 431 /* 432 * This is used during profiling to integrate system time. It can safely 433 * assume that the process is resident. 434 */ 435 #define PROC_PC(p) \ 436 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 437 438 /* 439 * Preempt the current process if in interrupt from user mode, 440 * or after the current trap/syscall if in system mode. 441 */ 442 void cpu_need_resched(struct cpu_info *, int); 443 444 /* 445 * Give a profiling tick to the current process when the user profiling 446 * buffer pages are invalid. On the MIPS, request an ast to send us 447 * through trap, marking the proc as needing a profiling tick. 448 */ 449 #define cpu_need_proftick(l) \ 450 do { \ 451 (l)->l_pflag |= LP_OWEUPC; \ 452 aston(l); \ 453 } while (/*CONSTCOND*/0) 454 455 /* 456 * Notify the current lwp (l) that it has a signal pending, 457 * process as soon as possible. 458 */ 459 #define cpu_signotify(l) aston(l) 460 461 #define aston(l) ((l)->l_md.md_astpending = 1) 462 463 /* 464 * Misc prototypes and variable declarations. 465 */ 466 struct lwp; 467 struct user; 468 469 extern struct segtab *segbase; /* current segtab base */ 470 extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */ 471 472 /* copy.S */ 473 int8_t ufetch_int8(void *); 474 int16_t ufetch_int16(void *); 475 int32_t ufetch_int32(void *); 476 uint8_t ufetch_uint8(void *); 477 uint16_t ufetch_uint16(void *); 478 uint32_t ufetch_uint32(void *); 479 int8_t ufetch_int8_intrsafe(void *); 480 int16_t ufetch_int16_intrsafe(void *); 481 int32_t ufetch_int32_intrsafe(void *); 482 uint8_t ufetch_uint8_intrsafe(void *); 483 uint16_t ufetch_uint16_intrsafe(void *); 484 uint32_t ufetch_uint32_intrsafe(void *); 485 #ifdef _LP64 486 int64_t ufetch_int64(void *); 487 uint64_t ufetch_uint64(void *); 488 int64_t ufetch_int64_intrsafe(void *); 489 uint64_t ufetch_uint64_intrsafe(void *); 490 #endif 491 char ufetch_char(void *); 492 short ufetch_short(void *); 493 int ufetch_int(void *); 494 long ufetch_long(void *); 495 char ufetch_char_intrsafe(void *); 496 short ufetch_short_intrsafe(void *); 497 int ufetch_int_intrsafe(void *); 498 long ufetch_long_intrsafe(void *); 499 500 u_char ufetch_uchar(void *); 501 u_short ufetch_ushort(void *); 502 u_int ufetch_uint(void *); 503 u_long ufetch_ulong(void *); 504 u_char ufetch_uchar_intrsafe(void *); 505 u_short ufetch_ushort_intrsafe(void *); 506 u_int ufetch_uint_intrsafe(void *); 507 u_long ufetch_ulong_intrsafe(void *); 508 void *ufetch_ptr(void *); 509 510 int ustore_int8(void *, int8_t); 511 int ustore_int16(void *, int16_t); 512 int ustore_int32(void *, int32_t); 513 int ustore_uint8(void *, uint8_t); 514 int ustore_uint16(void *, uint16_t); 515 int ustore_uint32(void *, uint32_t); 516 int ustore_int8_intrsafe(void *, int8_t); 517 int ustore_int16_intrsafe(void *, int16_t); 518 int ustore_int32_intrsafe(void *, int32_t); 519 int ustore_uint8_intrsafe(void *, uint8_t); 520 int ustore_uint16_intrsafe(void *, uint16_t); 521 int ustore_uint32_intrsafe(void *, uint32_t); 522 #ifdef _LP64 523 int ustore_int64(void *, int64_t); 524 int ustore_uint64(void *, uint64_t); 525 int ustore_int64_intrsafe(void *, int64_t); 526 int ustore_uint64_intrsafe(void *, uint64_t); 527 #endif 528 int ustore_char(void *, char); 529 int ustore_char_intrsafe(void *, char); 530 int ustore_short(void *, short); 531 int ustore_short_intrsafe(void *, short); 532 int ustore_int(void *, int); 533 int ustore_int_intrsafe(void *, int); 534 int ustore_long(void *, long); 535 int ustore_long_intrsafe(void *, long); 536 int ustore_uchar(void *, u_char); 537 int ustore_uchar_intrsafe(void *, u_char); 538 int ustore_ushort(void *, u_short); 539 int ustore_ushort_intrsafe(void *, u_short); 540 int ustore_uint(void *, u_int); 541 int ustore_uint_intrsafe(void *, u_int); 542 int ustore_ulong(void *, u_long); 543 int ustore_ulong_intrsafe(void *, u_long); 544 int ustore_ptr(void *, void *); 545 int ustore_ptr_intrsafe(void *, void *); 546 547 int ustore_uint32_isync(void *, uint32_t); 548 549 /* trap.c */ 550 void netintr(void); 551 int kdbpeek(vaddr_t); 552 553 /* mips_machdep.c */ 554 struct mips_vmfreelist; 555 struct phys_ram_seg; 556 void dumpsys(void); 557 int savectx(struct user *); 558 void mips_vector_init(void); 559 void mips_init_msgbuf(void); 560 void mips_init_lwp0_uarea(void); 561 void mips_page_physload(vaddr_t, vaddr_t, 562 const struct phys_ram_seg *, size_t, 563 const struct mips_vmfreelist *, size_t); 564 void savefpregs(struct lwp *); 565 void loadfpregs(struct lwp *); 566 void cpu_identify(device_t); 567 #ifdef MULTIPROCESSOR 568 void cpu_boot_secondary_processors(void); 569 #endif 570 571 /* locore*.S */ 572 int badaddr(void *, size_t); 573 int badaddr64(uint64_t, size_t); 574 575 /* vm_machdep.c */ 576 void cpu_uarea_remap(struct lwp *); 577 578 #endif /* ! _LOCORE */ 579 #endif /* _KERNEL */ 580 #endif /* _CPU_H_ */ 581
Indexes created Mon Oct 13 01:09:56 GMT 2025