cpu.h revision 1.90.16.26
1 /* $NetBSD: cpu.h,v 1.90.16.26 2010/03/11 08:16:59 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 48 #ifndef _LOCORE 49 #include <sys/cpu_data.h> 50 #include <sys/device.h> 51 #include <sys/evcnt.h> 52 53 #if defined(_KERNEL_OPT) 54 #include "opt_cputype.h" 55 #include "opt_lockdebug.h" 56 #include "opt_multiprocessor.h" 57 #endif 58 59 struct cpu_info { 60 struct cpu_data ci_data; /* MI per-cpu data */ 61 struct cpu_info *ci_next; /* Next CPU in list */ 62 struct cpu_softc *ci_softc; /* chip-dependent hook */ 63 device_t ci_dev; /* owning device */ 64 cpuid_t ci_cpuid; /* Machine-level identifier */ 65 u_long ci_cctr_freq; /* cycle counter frequency */ 66 u_long ci_cpu_freq; /* CPU frequency */ 67 u_long ci_cycles_per_hz; /* CPU freq / hz */ 68 u_long ci_divisor_delay; /* for delay/DELAY */ 69 u_long ci_divisor_recip; /* unused, for obsolete microtime(9) */ 70 struct lwp *ci_curlwp; /* currently running lwp */ 71 #ifndef NOFPU 72 struct lwp *ci_fpcurlwp; /* the current FPU owner */ 73 #endif 74 volatile int ci_want_resched; /* user preemption pending */ 75 int ci_mtx_count; /* negative count of held mutexes */ 76 int ci_mtx_oldspl; /* saved SPL value */ 77 int ci_idepth; /* hardware interrupt depth */ 78 int ci_cpl; /* current [interrupt] priority level */ 79 struct lwp *ci_softlwps[SOFTINT_COUNT]; 80 #define ci_softints ci_data.cpu_softints 81 /* 82 * Per-cpu pmap information 83 */ 84 int ci_tlb_slot; /* reserved tlb entry for cpu_info */ 85 struct pmap_tlb_info *ci_tlb_info; /* tlb information for this cpu */ 86 struct segtab *ci_pmap_segbase; 87 vaddr_t ci_pmap_srcbase; /* starting VA of ephemeral src space */ 88 vaddr_t ci_pmap_dstbase; /* starting VA of ephemeral dst space */ 89 #ifdef MULTIPROCESSOR 90 volatile u_long ci_flags; 91 uint64_t ci_active_ipis; /* bitmask of IPIs being serviced */ 92 uint32_t ci_ksp_tlb_slot; /* tlb entry for kernel stack */ 93 void *ci_fpsave_si; /* FP sync softint handler */ 94 struct evcnt ci_evcnt_all_ipis; /* aggregated IPI counter */ 95 struct evcnt ci_evcnt_per_ipi[NIPIS]; /* individual IPI counters*/ 96 97 #define CPUF_PRIMARY 0x01 /* CPU is primary CPU */ 98 #define CPUF_PRESENT 0x02 /* CPU is present */ 99 #define CPUF_RUNNING 0x04 /* CPU is running */ 100 #define CPUF_PAUSED 0x08 /* CPU is paused */ 101 #define CPUF_FPUSAVE 0x10 /* CPU is currently in fpusave_cpu() */ 102 #endif 103 }; 104 105 #define CPU_INFO_ITERATOR int 106 #define CPU_INFO_FOREACH(cii, ci) \ 107 (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next 108 109 #endif /* !_LOCORE */ 110 #endif /* _KERNEL */ 111 112 /* 113 * CTL_MACHDEP definitions. 114 */ 115 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 116 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 117 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 118 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 119 120 /* 121 * Platform can override, but note this breaks userland compatibility 122 * with other mips platforms. 123 */ 124 #ifndef CPU_MAXID 125 #define CPU_MAXID 5 /* number of valid machdep ids */ 126 #endif 127 128 #ifdef _KERNEL 129 #if defined(_LKM) || defined(_STANDALONE) 130 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 131 #define MIPS1 1 132 #define MIPS3 1 133 #define MIPS4 1 134 #define MIPS32 1 135 #define MIPS64 1 136 #endif 137 138 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 139 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 140 #endif 141 142 /* Shortcut for MIPS3 or above defined */ 143 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 144 #define MIPS3_PLUS 1 145 #define __HAVE_CPU_COUNTER 146 #else 147 #undef MIPS3_PLUS 148 #endif 149 150 /* 151 * Macros to find the CPU architecture we're on at run-time, 152 * or if possible, at compile-time. 153 */ 154 155 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 156 #define CPU_ARCH_MIPS1 (1 << 0) 157 #define CPU_ARCH_MIPS2 (1 << 1) 158 #define CPU_ARCH_MIPS3 (1 << 2) 159 #define CPU_ARCH_MIPS4 (1 << 3) 160 #define CPU_ARCH_MIPS5 (1 << 4) 161 #define CPU_ARCH_MIPS32 (1 << 5) 162 #define CPU_ARCH_MIPS64 (1 << 6) 163 164 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 165 #define MIPS_CURLWP $24 166 #define MIPS_CURLWP_QUOTED "$24" 167 #define MIPS_CURLWP_LABEL _L_T8 168 #define MIPS_CURLWP_REG _R_T8 169 #define TF_MIPS_CURLWP(x) TF_REG_T8(x) 170 171 #ifndef _LOCORE 172 173 extern struct cpu_info cpu_info_store; 174 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 175 176 #define curlwp mips_curlwp 177 #define curcpu() (curlwp->l_cpu) 178 #define curpcb (&curlwp->l_addr->u_pcb) 179 #ifdef MULTIPROCESSOR 180 #define cpu_number() (curcpu()->ci_cpuid) 181 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 182 #else 183 #define cpu_number() (0) 184 #endif 185 #define cpu_proc_fork(p1, p2) ((void)((p2)->p_md.md_abi = (p1)->p_md.md_abi)) 186 187 /* XXX simonb 188 * Should the following be in a cpu_info type structure? 189 * And how many of these are per-cpu vs. per-system? (Ie, 190 * we can assume that all cpus have the same mmu-type, but 191 * maybe not that all cpus run at the same clock speed. 192 * Some SGI's apparently support R12k and R14k in the same 193 * box.) 194 */ 195 struct mips_options { 196 const struct pridtab *mips_cpu; 197 198 u_int mips_cpu_arch; 199 u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */ 200 u_int mips_cpu_flags; 201 u_int mips_num_tlb_entries; 202 mips_prid_t mips_cpu_id; 203 mips_prid_t mips_fpu_id; 204 bool mips_has_r4k_mmu; 205 bool mips_has_llsc; 206 u_int mips3_pg_shift; 207 u_int mips3_pg_cached; 208 #ifdef MIPS3_PLUS 209 #ifdef _LP64 210 uint64_t mips3_xkphys_cached; 211 #endif 212 uint64_t mips3_tlb_vpn_mask; 213 uint64_t mips3_tlb_pfn_mask; 214 uint32_t mips3_tlb_pg_mask; 215 #endif 216 }; 217 extern struct mips_options mips_options; 218 219 #define CPU_MIPS_R4K_MMU 0x0001 220 #define CPU_MIPS_NO_LLSC 0x0002 221 #define CPU_MIPS_CAUSE_IV 0x0004 222 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 223 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 224 #define CPU_MIPS_CACHED_CCA_SHIFT 4 225 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 226 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 227 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 228 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 229 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 230 #define CPU_MIPS_NO_LLADDR 0x1000 231 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 232 #define MIPS_NOT_SUPP 0x8000 233 234 #endif /* !_LOCORE */ 235 236 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE) 237 238 #if defined(MIPS1) 239 240 # define CPUISMIPS3 0 241 # define CPUIS64BITS 0 242 # define CPUISMIPS32 0 243 # define CPUISMIPS64 0 244 # define CPUISMIPSNN 0 245 # define MIPS_HAS_R4K_MMU 0 246 # define MIPS_HAS_CLOCK 0 247 # define MIPS_HAS_LLSC 0 248 # define MIPS_HAS_LLADDR 0 249 250 #elif defined(MIPS3) || defined(MIPS4) 251 252 # define CPUISMIPS3 1 253 # define CPUIS64BITS 1 254 # define CPUISMIPS32 0 255 # define CPUISMIPS64 0 256 # define CPUISMIPSNN 0 257 # define MIPS_HAS_R4K_MMU 1 258 # define MIPS_HAS_CLOCK 1 259 # if defined(_LOCORE) 260 # if !defined(MIPS3_5900) && !defined(MIPS3_4100) 261 # define MIPS_HAS_LLSC 1 262 # else 263 # define MIPS_HAS_LLSC 0 264 # endif 265 # else /* _LOCORE */ 266 # define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 267 # endif /* _LOCORE */ 268 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 269 270 #elif defined(MIPS32) 271 272 # define CPUISMIPS3 1 273 # define CPUIS64BITS 0 274 # define CPUISMIPS32 1 275 # define CPUISMIPS64 0 276 # define CPUISMIPSNN 1 277 # define MIPS_HAS_R4K_MMU 1 278 # define MIPS_HAS_CLOCK 1 279 # define MIPS_HAS_LLSC 1 280 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 281 282 #elif defined(MIPS64) 283 284 # define CPUISMIPS3 1 285 # define CPUIS64BITS 1 286 # define CPUISMIPS32 0 287 # define CPUISMIPS64 1 288 # define CPUISMIPSNN 1 289 # define MIPS_HAS_R4K_MMU 1 290 # define MIPS_HAS_CLOCK 1 291 # define MIPS_HAS_LLSC 1 292 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 293 294 #endif 295 296 #else /* run-time test */ 297 298 #ifndef _LOCORE 299 300 #define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu) 301 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 302 #define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 303 304 /* This test is ... rather bogus */ 305 #define CPUISMIPS3 ((mips_options.mips_cpu_arch & \ 306 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 307 308 /* And these aren't much better while the previous test exists as is... */ 309 #define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0) 310 #define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0) 311 #define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0) 312 #define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0) 313 #define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 314 #define CPUIS64BITS ((mips_options.mips_cpu_arch & \ 315 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 316 317 #define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) 318 319 #else /* !_LOCORE */ 320 321 #define MIPS_HAS_LLSC 0 322 323 #endif /* !_LOCORE */ 324 325 #endif /* run-time test */ 326 327 #ifndef _LOCORE 328 329 /* 330 * definitions of cpu-dependent requirements 331 * referenced in generic code 332 */ 333 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 334 335 /* 336 * Send an inter-processor interupt to another CPU. 337 */ 338 int cpu_send_ipi(struct cpu_info *, int); 339 340 /* 341 * cpu_intr(ppl, pc, status); (most state needed by clockframe) 342 */ 343 void cpu_intr(int, vaddr_t, uint32_t); 344 345 /* 346 * Arguments to hardclock and gatherstats encapsulate the previous 347 * machine state in an opaque clockframe. 348 */ 349 struct clockframe { 350 vaddr_t pc; /* program counter at time of interrupt */ 351 uint32_t sr; /* status register at time of interrupt */ 352 bool intr; /* interrupted a interrupt */ 353 }; 354 355 /* 356 * A port must provde CLKF_USERMODE() for use in machine-independent code. 357 * These differ on r4000 and r3000 systems; provide them in the 358 * port-dependent file that includes this one, using the macros below. 359 */ 360 361 /* mips1 versions */ 362 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 363 364 /* mips3 versions */ 365 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 366 367 #define CLKF_PC(framep) ((framep)->pc) 368 #define CLKF_INTR(framep) ((framep)->intr) 369 370 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 371 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 372 #endif 373 374 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 375 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 376 #endif 377 378 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 379 #define CLKF_USERMODE(framep) \ 380 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 381 #endif 382 383 /* 384 * Misc prototypes and variable declarations. 385 */ 386 struct lwp; 387 struct user; 388 389 /* 390 * Preempt the current process if in interrupt from user mode, 391 * or after the current trap/syscall if in system mode. 392 */ 393 void cpu_need_resched(struct cpu_info *, int); 394 /* 395 * Notify the current lwp (l) that it has a signal pending, 396 * process as soon as possible. 397 */ 398 void cpu_signotify(struct lwp *); 399 400 /* 401 * Give a profiling tick to the current process when the user profiling 402 * buffer pages are invalid. On the MIPS, request an ast to send us 403 * through trap, marking the proc as needing a profiling tick. 404 */ 405 void cpu_need_proftick(struct lwp *); 406 void cpu_set_curpri(int); 407 408 extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */ 409 410 /* cpu_subr.c */ 411 #ifdef MULTIPROCESSOR 412 extern volatile u_long cpus_running; 413 extern volatile u_long cpus_hatched; 414 extern volatile u_long cpus_halted; 415 #endif 416 417 struct cpu_info * 418 cpu_info_alloc(struct pmap_tlb_info *, u_int); 419 void cpu_attach_common(device_t, struct cpu_info *); 420 void cpu_startup_common(void); 421 #ifdef MULTIPROCESSOR 422 void cpu_hatch(struct cpu_info *ci); 423 void cpu_trampoline(void); 424 void cpu_boot_secondary_processors(void); 425 #endif 426 427 /* copy.S */ 428 int8_t ufetch_int8(void *); 429 int16_t ufetch_int16(void *); 430 int32_t ufetch_int32(void *); 431 uint8_t ufetch_uint8(void *); 432 uint16_t ufetch_uint16(void *); 433 uint32_t ufetch_uint32(void *); 434 int8_t ufetch_int8_intrsafe(void *); 435 int16_t ufetch_int16_intrsafe(void *); 436 int32_t ufetch_int32_intrsafe(void *); 437 uint8_t ufetch_uint8_intrsafe(void *); 438 uint16_t ufetch_uint16_intrsafe(void *); 439 uint32_t ufetch_uint32_intrsafe(void *); 440 #ifdef _LP64 441 int64_t ufetch_int64(void *); 442 uint64_t ufetch_uint64(void *); 443 int64_t ufetch_int64_intrsafe(void *); 444 uint64_t ufetch_uint64_intrsafe(void *); 445 #endif 446 char ufetch_char(void *); 447 short ufetch_short(void *); 448 int ufetch_int(void *); 449 long ufetch_long(void *); 450 char ufetch_char_intrsafe(void *); 451 short ufetch_short_intrsafe(void *); 452 int ufetch_int_intrsafe(void *); 453 long ufetch_long_intrsafe(void *); 454 455 u_char ufetch_uchar(void *); 456 u_short ufetch_ushort(void *); 457 u_int ufetch_uint(void *); 458 u_long ufetch_ulong(void *); 459 u_char ufetch_uchar_intrsafe(void *); 460 u_short ufetch_ushort_intrsafe(void *); 461 u_int ufetch_uint_intrsafe(void *); 462 u_long ufetch_ulong_intrsafe(void *); 463 void *ufetch_ptr(void *); 464 465 int ustore_int8(void *, int8_t); 466 int ustore_int16(void *, int16_t); 467 int ustore_int32(void *, int32_t); 468 int ustore_uint8(void *, uint8_t); 469 int ustore_uint16(void *, uint16_t); 470 int ustore_uint32(void *, uint32_t); 471 int ustore_int8_intrsafe(void *, int8_t); 472 int ustore_int16_intrsafe(void *, int16_t); 473 int ustore_int32_intrsafe(void *, int32_t); 474 int ustore_uint8_intrsafe(void *, uint8_t); 475 int ustore_uint16_intrsafe(void *, uint16_t); 476 int ustore_uint32_intrsafe(void *, uint32_t); 477 #ifdef _LP64 478 int ustore_int64(void *, int64_t); 479 int ustore_uint64(void *, uint64_t); 480 int ustore_int64_intrsafe(void *, int64_t); 481 int ustore_uint64_intrsafe(void *, uint64_t); 482 #endif 483 int ustore_char(void *, char); 484 int ustore_char_intrsafe(void *, char); 485 int ustore_short(void *, short); 486 int ustore_short_intrsafe(void *, short); 487 int ustore_int(void *, int); 488 int ustore_int_intrsafe(void *, int); 489 int ustore_long(void *, long); 490 int ustore_long_intrsafe(void *, long); 491 int ustore_uchar(void *, u_char); 492 int ustore_uchar_intrsafe(void *, u_char); 493 int ustore_ushort(void *, u_short); 494 int ustore_ushort_intrsafe(void *, u_short); 495 int ustore_uint(void *, u_int); 496 int ustore_uint_intrsafe(void *, u_int); 497 int ustore_ulong(void *, u_long); 498 int ustore_ulong_intrsafe(void *, u_long); 499 int ustore_ptr(void *, void *); 500 int ustore_ptr_intrsafe(void *, void *); 501 502 int ustore_uint32_isync(void *, uint32_t); 503 504 /* trap.c */ 505 void netintr(void); 506 int kdbpeek(vaddr_t); 507 508 /* mips_fpu.c */ 509 void fpu_init(void); 510 void fpudiscard_lwp(struct lwp *); 511 void fpuload_lwp(struct lwp *); 512 void fpusave_lwp(struct lwp *); 513 void fpusave_cpu(struct cpu_info *); 514 515 /* mips_machdep.c */ 516 struct mips_vmfreelist; 517 struct phys_ram_seg; 518 void dumpsys(void); 519 int savectx(struct user *); 520 void mips_vector_init(void); 521 void mips_init_msgbuf(void); 522 void mips_init_lwp0_uarea(void); 523 void mips_page_physload(vaddr_t, vaddr_t, 524 const struct phys_ram_seg *, size_t, 525 const struct mips_vmfreelist *, size_t); 526 void cpu_identify(device_t); 527 528 /* locore*.S */ 529 int badaddr(void *, size_t); 530 int badaddr64(uint64_t, size_t); 531 532 /* vm_machdep.c */ 533 void cpu_uarea_remap(struct lwp *); 534 535 #endif /* ! _LOCORE */ 536 #endif /* _KERNEL */ 537 #endif /* _CPU_H_ */ 538
Indexes created Tue Oct 14 11:09:46 GMT 2025