cpu.h revision 1.90.16.27
1 /* $NetBSD: cpu.h,v 1.90.16.27 2010/03/11 08:19:01 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 48 #ifndef _LOCORE 49 #include <sys/cpu_data.h> 50 #include <sys/device.h> 51 #include <sys/evcnt.h> 52 53 #if defined(_KERNEL_OPT) 54 #include "opt_cputype.h" 55 #include "opt_lockdebug.h" 56 #include "opt_multiprocessor.h" 57 #endif 58 59 struct cpu_info { 60 struct cpu_data ci_data; /* MI per-cpu data */ 61 struct cpu_info *ci_next; /* Next CPU in list */ 62 struct cpu_softc *ci_softc; /* chip-dependent hook */ 63 device_t ci_dev; /* owning device */ 64 cpuid_t ci_cpuid; /* Machine-level identifier */ 65 u_long ci_cctr_freq; /* cycle counter frequency */ 66 u_long ci_cpu_freq; /* CPU frequency */ 67 u_long ci_cycles_per_hz; /* CPU freq / hz */ 68 u_long ci_divisor_delay; /* for delay/DELAY */ 69 u_long ci_divisor_recip; /* unused, for obsolete microtime(9) */ 70 struct lwp *ci_curlwp; /* currently running lwp */ 71 #ifndef NOFPU 72 struct lwp *ci_fpcurlwp; /* the current FPU owner */ 73 #endif 74 volatile int ci_want_resched; /* user preemption pending */ 75 int ci_mtx_count; /* negative count of held mutexes */ 76 int ci_mtx_oldspl; /* saved SPL value */ 77 int ci_idepth; /* hardware interrupt depth */ 78 int ci_cpl; /* current [interrupt] priority level */ 79 struct lwp *ci_softlwps[SOFTINT_COUNT]; 80 #define ci_softints ci_data.cpu_softints 81 /* 82 * Per-cpu pmap information 83 */ 84 int ci_tlb_slot; /* reserved tlb entry for cpu_info */ 85 struct pmap_tlb_info *ci_tlb_info; /* tlb information for this cpu */ 86 struct segtab *ci_pmap_segbase; 87 vaddr_t ci_pmap_srcbase; /* starting VA of ephemeral src space */ 88 vaddr_t ci_pmap_dstbase; /* starting VA of ephemeral dst space */ 89 #ifdef MULTIPROCESSOR 90 volatile u_long ci_flags; 91 uint64_t ci_active_ipis; /* bitmask of IPIs being serviced */ 92 uint32_t ci_ksp_tlb_slot; /* tlb entry for kernel stack */ 93 void *ci_fpsave_si; /* FP sync softint handler */ 94 struct evcnt ci_evcnt_all_ipis; /* aggregated IPI counter */ 95 struct evcnt ci_evcnt_per_ipi[NIPIS]; /* individual IPI counters*/ 96 struct evcnt ci_evcnt_synci_activate_rqst; 97 struct evcnt ci_evcnt_synci_onproc_rqst; 98 struct evcnt ci_evcnt_synci_deferred_rqst; 99 struct evcnt ci_evcnt_synci_ipi_rqst; 100 101 #define CPUF_PRIMARY 0x01 /* CPU is primary CPU */ 102 #define CPUF_PRESENT 0x02 /* CPU is present */ 103 #define CPUF_RUNNING 0x04 /* CPU is running */ 104 #define CPUF_PAUSED 0x08 /* CPU is paused */ 105 #define CPUF_FPUSAVE 0x10 /* CPU is currently in fpusave_cpu() */ 106 #define CPUF_USERPMAP 0x20 /* CPU has a user pmap activated */ 107 #endif 108 }; 109 110 #define CPU_INFO_ITERATOR int 111 #define CPU_INFO_FOREACH(cii, ci) \ 112 (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next 113 114 #endif /* !_LOCORE */ 115 #endif /* _KERNEL */ 116 117 /* 118 * CTL_MACHDEP definitions. 119 */ 120 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 121 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 122 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 123 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 124 125 /* 126 * Platform can override, but note this breaks userland compatibility 127 * with other mips platforms. 128 */ 129 #ifndef CPU_MAXID 130 #define CPU_MAXID 5 /* number of valid machdep ids */ 131 #endif 132 133 #ifdef _KERNEL 134 #if defined(_LKM) || defined(_STANDALONE) 135 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 136 #define MIPS1 1 137 #define MIPS3 1 138 #define MIPS4 1 139 #define MIPS32 1 140 #define MIPS64 1 141 #endif 142 143 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 144 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 145 #endif 146 147 /* Shortcut for MIPS3 or above defined */ 148 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 149 #define MIPS3_PLUS 1 150 #define __HAVE_CPU_COUNTER 151 #else 152 #undef MIPS3_PLUS 153 #endif 154 155 /* 156 * Macros to find the CPU architecture we're on at run-time, 157 * or if possible, at compile-time. 158 */ 159 160 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 161 #define CPU_ARCH_MIPS1 (1 << 0) 162 #define CPU_ARCH_MIPS2 (1 << 1) 163 #define CPU_ARCH_MIPS3 (1 << 2) 164 #define CPU_ARCH_MIPS4 (1 << 3) 165 #define CPU_ARCH_MIPS5 (1 << 4) 166 #define CPU_ARCH_MIPS32 (1 << 5) 167 #define CPU_ARCH_MIPS64 (1 << 6) 168 169 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 170 #define MIPS_CURLWP $24 171 #define MIPS_CURLWP_QUOTED "$24" 172 #define MIPS_CURLWP_LABEL _L_T8 173 #define MIPS_CURLWP_REG _R_T8 174 #define TF_MIPS_CURLWP(x) TF_REG_T8(x) 175 176 #ifndef _LOCORE 177 178 extern struct cpu_info cpu_info_store; 179 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 180 181 #define curlwp mips_curlwp 182 #define curcpu() (curlwp->l_cpu) 183 #define curpcb (&curlwp->l_addr->u_pcb) 184 #ifdef MULTIPROCESSOR 185 #define cpu_number() (curcpu()->ci_cpuid) 186 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 187 #else 188 #define cpu_number() (0) 189 #endif 190 #define cpu_proc_fork(p1, p2) ((void)((p2)->p_md.md_abi = (p1)->p_md.md_abi)) 191 192 /* XXX simonb 193 * Should the following be in a cpu_info type structure? 194 * And how many of these are per-cpu vs. per-system? (Ie, 195 * we can assume that all cpus have the same mmu-type, but 196 * maybe not that all cpus run at the same clock speed. 197 * Some SGI's apparently support R12k and R14k in the same 198 * box.) 199 */ 200 struct mips_options { 201 const struct pridtab *mips_cpu; 202 203 u_int mips_cpu_arch; 204 u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */ 205 u_int mips_cpu_flags; 206 u_int mips_num_tlb_entries; 207 mips_prid_t mips_cpu_id; 208 mips_prid_t mips_fpu_id; 209 bool mips_has_r4k_mmu; 210 bool mips_has_llsc; 211 u_int mips3_pg_shift; 212 u_int mips3_pg_cached; 213 #ifdef MIPS3_PLUS 214 #ifdef _LP64 215 uint64_t mips3_xkphys_cached; 216 #endif 217 uint64_t mips3_tlb_vpn_mask; 218 uint64_t mips3_tlb_pfn_mask; 219 uint32_t mips3_tlb_pg_mask; 220 #endif 221 }; 222 extern struct mips_options mips_options; 223 224 #define CPU_MIPS_R4K_MMU 0x0001 225 #define CPU_MIPS_NO_LLSC 0x0002 226 #define CPU_MIPS_CAUSE_IV 0x0004 227 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 228 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 229 #define CPU_MIPS_CACHED_CCA_SHIFT 4 230 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 231 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 232 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 233 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 234 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 235 #define CPU_MIPS_NO_LLADDR 0x1000 236 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 237 #define MIPS_NOT_SUPP 0x8000 238 239 #endif /* !_LOCORE */ 240 241 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE) 242 243 #if defined(MIPS1) 244 245 # define CPUISMIPS3 0 246 # define CPUIS64BITS 0 247 # define CPUISMIPS32 0 248 # define CPUISMIPS64 0 249 # define CPUISMIPSNN 0 250 # define MIPS_HAS_R4K_MMU 0 251 # define MIPS_HAS_CLOCK 0 252 # define MIPS_HAS_LLSC 0 253 # define MIPS_HAS_LLADDR 0 254 255 #elif defined(MIPS3) || defined(MIPS4) 256 257 # define CPUISMIPS3 1 258 # define CPUIS64BITS 1 259 # define CPUISMIPS32 0 260 # define CPUISMIPS64 0 261 # define CPUISMIPSNN 0 262 # define MIPS_HAS_R4K_MMU 1 263 # define MIPS_HAS_CLOCK 1 264 # if defined(_LOCORE) 265 # if !defined(MIPS3_5900) && !defined(MIPS3_4100) 266 # define MIPS_HAS_LLSC 1 267 # else 268 # define MIPS_HAS_LLSC 0 269 # endif 270 # else /* _LOCORE */ 271 # define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 272 # endif /* _LOCORE */ 273 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 274 275 #elif defined(MIPS32) 276 277 # define CPUISMIPS3 1 278 # define CPUIS64BITS 0 279 # define CPUISMIPS32 1 280 # define CPUISMIPS64 0 281 # define CPUISMIPSNN 1 282 # define MIPS_HAS_R4K_MMU 1 283 # define MIPS_HAS_CLOCK 1 284 # define MIPS_HAS_LLSC 1 285 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 286 287 #elif defined(MIPS64) 288 289 # define CPUISMIPS3 1 290 # define CPUIS64BITS 1 291 # define CPUISMIPS32 0 292 # define CPUISMIPS64 1 293 # define CPUISMIPSNN 1 294 # define MIPS_HAS_R4K_MMU 1 295 # define MIPS_HAS_CLOCK 1 296 # define MIPS_HAS_LLSC 1 297 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 298 299 #endif 300 301 #else /* run-time test */ 302 303 #ifndef _LOCORE 304 305 #define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu) 306 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 307 #define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 308 309 /* This test is ... rather bogus */ 310 #define CPUISMIPS3 ((mips_options.mips_cpu_arch & \ 311 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 312 313 /* And these aren't much better while the previous test exists as is... */ 314 #define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0) 315 #define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0) 316 #define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0) 317 #define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0) 318 #define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 319 #define CPUIS64BITS ((mips_options.mips_cpu_arch & \ 320 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 321 322 #define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) 323 324 #else /* !_LOCORE */ 325 326 #define MIPS_HAS_LLSC 0 327 328 #endif /* !_LOCORE */ 329 330 #endif /* run-time test */ 331 332 #ifndef _LOCORE 333 334 /* 335 * definitions of cpu-dependent requirements 336 * referenced in generic code 337 */ 338 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 339 340 /* 341 * Send an inter-processor interupt to another CPU. 342 */ 343 int cpu_send_ipi(struct cpu_info *, int); 344 345 /* 346 * cpu_intr(ppl, pc, status); (most state needed by clockframe) 347 */ 348 void cpu_intr(int, vaddr_t, uint32_t); 349 350 /* 351 * Arguments to hardclock and gatherstats encapsulate the previous 352 * machine state in an opaque clockframe. 353 */ 354 struct clockframe { 355 vaddr_t pc; /* program counter at time of interrupt */ 356 uint32_t sr; /* status register at time of interrupt */ 357 bool intr; /* interrupted a interrupt */ 358 }; 359 360 /* 361 * A port must provde CLKF_USERMODE() for use in machine-independent code. 362 * These differ on r4000 and r3000 systems; provide them in the 363 * port-dependent file that includes this one, using the macros below. 364 */ 365 366 /* mips1 versions */ 367 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 368 369 /* mips3 versions */ 370 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 371 372 #define CLKF_PC(framep) ((framep)->pc) 373 #define CLKF_INTR(framep) ((framep)->intr) 374 375 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 376 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 377 #endif 378 379 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 380 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 381 #endif 382 383 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 384 #define CLKF_USERMODE(framep) \ 385 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 386 #endif 387 388 /* 389 * Misc prototypes and variable declarations. 390 */ 391 struct lwp; 392 struct user; 393 394 /* 395 * Preempt the current process if in interrupt from user mode, 396 * or after the current trap/syscall if in system mode. 397 */ 398 void cpu_need_resched(struct cpu_info *, int); 399 /* 400 * Notify the current lwp (l) that it has a signal pending, 401 * process as soon as possible. 402 */ 403 void cpu_signotify(struct lwp *); 404 405 /* 406 * Give a profiling tick to the current process when the user profiling 407 * buffer pages are invalid. On the MIPS, request an ast to send us 408 * through trap, marking the proc as needing a profiling tick. 409 */ 410 void cpu_need_proftick(struct lwp *); 411 void cpu_set_curpri(int); 412 413 extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */ 414 415 /* cpu_subr.c */ 416 #ifdef MULTIPROCESSOR 417 extern volatile u_long cpus_running; 418 extern volatile u_long cpus_hatched; 419 extern volatile u_long cpus_halted; 420 #endif 421 422 struct cpu_info * 423 cpu_info_alloc(struct pmap_tlb_info *, u_int); 424 void cpu_attach_common(device_t, struct cpu_info *); 425 void cpu_startup_common(void); 426 #ifdef MULTIPROCESSOR 427 void cpu_hatch(struct cpu_info *ci); 428 void cpu_trampoline(void); 429 void cpu_boot_secondary_processors(void); 430 #endif 431 432 /* copy.S */ 433 int8_t ufetch_int8(void *); 434 int16_t ufetch_int16(void *); 435 int32_t ufetch_int32(void *); 436 uint8_t ufetch_uint8(void *); 437 uint16_t ufetch_uint16(void *); 438 uint32_t ufetch_uint32(void *); 439 int8_t ufetch_int8_intrsafe(void *); 440 int16_t ufetch_int16_intrsafe(void *); 441 int32_t ufetch_int32_intrsafe(void *); 442 uint8_t ufetch_uint8_intrsafe(void *); 443 uint16_t ufetch_uint16_intrsafe(void *); 444 uint32_t ufetch_uint32_intrsafe(void *); 445 #ifdef _LP64 446 int64_t ufetch_int64(void *); 447 uint64_t ufetch_uint64(void *); 448 int64_t ufetch_int64_intrsafe(void *); 449 uint64_t ufetch_uint64_intrsafe(void *); 450 #endif 451 char ufetch_char(void *); 452 short ufetch_short(void *); 453 int ufetch_int(void *); 454 long ufetch_long(void *); 455 char ufetch_char_intrsafe(void *); 456 short ufetch_short_intrsafe(void *); 457 int ufetch_int_intrsafe(void *); 458 long ufetch_long_intrsafe(void *); 459 460 u_char ufetch_uchar(void *); 461 u_short ufetch_ushort(void *); 462 u_int ufetch_uint(void *); 463 u_long ufetch_ulong(void *); 464 u_char ufetch_uchar_intrsafe(void *); 465 u_short ufetch_ushort_intrsafe(void *); 466 u_int ufetch_uint_intrsafe(void *); 467 u_long ufetch_ulong_intrsafe(void *); 468 void *ufetch_ptr(void *); 469 470 int ustore_int8(void *, int8_t); 471 int ustore_int16(void *, int16_t); 472 int ustore_int32(void *, int32_t); 473 int ustore_uint8(void *, uint8_t); 474 int ustore_uint16(void *, uint16_t); 475 int ustore_uint32(void *, uint32_t); 476 int ustore_int8_intrsafe(void *, int8_t); 477 int ustore_int16_intrsafe(void *, int16_t); 478 int ustore_int32_intrsafe(void *, int32_t); 479 int ustore_uint8_intrsafe(void *, uint8_t); 480 int ustore_uint16_intrsafe(void *, uint16_t); 481 int ustore_uint32_intrsafe(void *, uint32_t); 482 #ifdef _LP64 483 int ustore_int64(void *, int64_t); 484 int ustore_uint64(void *, uint64_t); 485 int ustore_int64_intrsafe(void *, int64_t); 486 int ustore_uint64_intrsafe(void *, uint64_t); 487 #endif 488 int ustore_char(void *, char); 489 int ustore_char_intrsafe(void *, char); 490 int ustore_short(void *, short); 491 int ustore_short_intrsafe(void *, short); 492 int ustore_int(void *, int); 493 int ustore_int_intrsafe(void *, int); 494 int ustore_long(void *, long); 495 int ustore_long_intrsafe(void *, long); 496 int ustore_uchar(void *, u_char); 497 int ustore_uchar_intrsafe(void *, u_char); 498 int ustore_ushort(void *, u_short); 499 int ustore_ushort_intrsafe(void *, u_short); 500 int ustore_uint(void *, u_int); 501 int ustore_uint_intrsafe(void *, u_int); 502 int ustore_ulong(void *, u_long); 503 int ustore_ulong_intrsafe(void *, u_long); 504 int ustore_ptr(void *, void *); 505 int ustore_ptr_intrsafe(void *, void *); 506 507 int ustore_uint32_isync(void *, uint32_t); 508 509 /* trap.c */ 510 void netintr(void); 511 int kdbpeek(vaddr_t); 512 513 /* mips_fpu.c */ 514 void fpu_init(void); 515 void fpudiscard_lwp(struct lwp *); 516 void fpuload_lwp(struct lwp *); 517 void fpusave_lwp(struct lwp *); 518 void fpusave_cpu(struct cpu_info *); 519 520 /* mips_machdep.c */ 521 struct mips_vmfreelist; 522 struct phys_ram_seg; 523 void dumpsys(void); 524 int savectx(struct user *); 525 void mips_vector_init(void); 526 void mips_init_msgbuf(void); 527 void mips_init_lwp0_uarea(void); 528 void mips_page_physload(vaddr_t, vaddr_t, 529 const struct phys_ram_seg *, size_t, 530 const struct mips_vmfreelist *, size_t); 531 void cpu_identify(device_t); 532 533 /* locore*.S */ 534 int badaddr(void *, size_t); 535 int badaddr64(uint64_t, size_t); 536 537 /* vm_machdep.c */ 538 void cpu_uarea_remap(struct lwp *); 539 540 #endif /* ! _LOCORE */ 541 #endif /* _KERNEL */ 542 #endif /* _CPU_H_ */ 543
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