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cpu.h revision 1.90.16.28
      1 /*	$NetBSD: cpu.h,v 1.90.16.28 2010/03/21 18:17:21 cliff Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1992, 1993
      5  *	The Regents of the University of California.  All rights reserved.
      6  *
      7  * This code is derived from software contributed to Berkeley by
      8  * Ralph Campbell and Rick Macklem.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. Neither the name of the University nor the names of its contributors
     19  *    may be used to endorse or promote products derived from this software
     20  *    without specific prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  * SUCH DAMAGE.
     33  *
     34  *	@(#)cpu.h	8.4 (Berkeley) 1/4/94
     35  */
     36 
     37 #ifndef _CPU_H_
     38 #define _CPU_H_
     39 
     40 #include <mips/cpuregs.h>
     41 
     42 /*
     43  * Exported definitions unique to NetBSD/mips cpu support.
     44  */
     45 
     46 #ifdef _KERNEL
     47 
     48 #ifndef _LOCORE
     49 #include <sys/cpu_data.h>
     50 #include <sys/device.h>
     51 #include <sys/evcnt.h>
     52 
     53 #if defined(_KERNEL_OPT)
     54 #include "opt_cputype.h"
     55 #include "opt_lockdebug.h"
     56 #include "opt_multiprocessor.h"
     57 #endif
     58 
     59 struct cpu_info {
     60 	struct cpu_data ci_data;	/* MI per-cpu data */
     61 	struct cpu_info *ci_next;	/* Next CPU in list */
     62 	struct cpu_softc *ci_softc;	/* chip-dependent hook */
     63 	device_t ci_dev;		/* owning device */
     64 	cpuid_t ci_cpuid;		/* Machine-level identifier */
     65 	u_long ci_cctr_freq;		/* cycle counter frequency */
     66 	u_long ci_cpu_freq;		/* CPU frequency */
     67 	u_long ci_cycles_per_hz;	/* CPU freq / hz */
     68 	u_long ci_divisor_delay;	/* for delay/DELAY */
     69 	u_long ci_divisor_recip;	/* unused, for obsolete microtime(9) */
     70 	struct lwp *ci_curlwp;		/* currently running lwp */
     71 #ifndef NOFPU
     72 	struct lwp *ci_fpcurlwp;	/* the current FPU owner */
     73 #endif
     74 	volatile int ci_want_resched;	/* user preemption pending */
     75 	int ci_mtx_count;		/* negative count of held mutexes */
     76 	int ci_mtx_oldspl;		/* saved SPL value */
     77 	int ci_idepth;			/* hardware interrupt depth */
     78 	int ci_cpl;			/* current [interrupt] priority level */
     79 	uint32_t ci_next_cp0_clk_intr;	/* for hard clock intr scheduling */
     80 	struct evcnt ci_count_compare_evcnt;		/* hard clock intr counter */
     81 	struct evcnt ci_count_compare_missed_evcnt;	/* hard clock miss counter */
     82 	struct lwp *ci_softlwps[SOFTINT_COUNT];
     83 #define	ci_softints	ci_data.cpu_softints
     84 
     85 	/*
     86 	 * Per-cpu pmap information
     87 	 */
     88 	int ci_tlb_slot;		/* reserved tlb entry for cpu_info */
     89 	struct pmap_tlb_info *ci_tlb_info; /* tlb information for this cpu */
     90 	struct segtab *ci_pmap_segbase;
     91 	vaddr_t ci_pmap_srcbase;	/* starting VA of ephemeral src space */
     92 	vaddr_t ci_pmap_dstbase;	/* starting VA of ephemeral dst space */
     93 
     94 
     95 #ifdef MULTIPROCESSOR
     96 	volatile u_long ci_flags;
     97 	volatile uint64_t ci_request_ipis;
     98 					/* bitmask of IPIs requested */
     99 					/*  use on chips where hw cannot pass tag */
    100 	uint64_t ci_active_ipis;	/* bitmask of IPIs being serviced */
    101 	uint32_t ci_ksp_tlb_slot;	/* tlb entry for kernel stack */
    102 	void *ci_fpsave_si;		/* FP sync softint handler */
    103 	struct evcnt ci_evcnt_all_ipis;	/* aggregated IPI counter */
    104 	struct evcnt ci_evcnt_per_ipi[NIPIS];	/* individual IPI counters*/
    105 	struct evcnt ci_evcnt_synci_activate_rqst;
    106 	struct evcnt ci_evcnt_synci_onproc_rqst;
    107 	struct evcnt ci_evcnt_synci_deferred_rqst;
    108 	struct evcnt ci_evcnt_synci_ipi_rqst;
    109 
    110 #define	CPUF_PRIMARY	0x01		/* CPU is primary CPU */
    111 #define	CPUF_PRESENT	0x02		/* CPU is present */
    112 #define	CPUF_RUNNING	0x04		/* CPU is running */
    113 #define	CPUF_PAUSED	0x08		/* CPU is paused */
    114 #define	CPUF_FPUSAVE	0x10		/* CPU is currently in fpusave_cpu() */
    115 #define	CPUF_USERPMAP	0x20		/* CPU has a user pmap activated */
    116 #endif
    117 
    118 };
    119 
    120 #define	CPU_INFO_ITERATOR		int
    121 #define	CPU_INFO_FOREACH(cii, ci)	\
    122     (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next
    123 
    124 #endif /* !_LOCORE */
    125 #endif /* _KERNEL */
    126 
    127 /*
    128  * CTL_MACHDEP definitions.
    129  */
    130 #define CPU_CONSDEV		1	/* dev_t: console terminal device */
    131 #define CPU_BOOTED_KERNEL	2	/* string: booted kernel name */
    132 #define CPU_ROOT_DEVICE		3	/* string: root device name */
    133 #define CPU_LLSC		4	/* OS/CPU supports LL/SC instruction */
    134 
    135 /*
    136  * Platform can override, but note this breaks userland compatibility
    137  * with other mips platforms.
    138  */
    139 #ifndef CPU_MAXID
    140 #define CPU_MAXID		5	/* number of valid machdep ids */
    141 #endif
    142 
    143 #ifdef _KERNEL
    144 #if defined(_LKM) || defined(_STANDALONE)
    145 /* Assume all CPU architectures are valid for LKM's and standlone progs */
    146 #define	MIPS1	1
    147 #define	MIPS3	1
    148 #define	MIPS4	1
    149 #define	MIPS32	1
    150 #define	MIPS64	1
    151 #endif
    152 
    153 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0
    154 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified
    155 #endif
    156 
    157 /* Shortcut for MIPS3 or above defined */
    158 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)
    159 #define	MIPS3_PLUS	1
    160 #define __HAVE_CPU_COUNTER
    161 #else
    162 #undef MIPS3_PLUS
    163 #endif
    164 
    165 /*
    166  * Macros to find the CPU architecture we're on at run-time,
    167  * or if possible, at compile-time.
    168  */
    169 
    170 #define	CPU_ARCH_MIPSx	0		/* XXX unknown */
    171 #define	CPU_ARCH_MIPS1	(1 << 0)
    172 #define	CPU_ARCH_MIPS2	(1 << 1)
    173 #define	CPU_ARCH_MIPS3	(1 << 2)
    174 #define	CPU_ARCH_MIPS4	(1 << 3)
    175 #define	CPU_ARCH_MIPS5	(1 << 4)
    176 #define	CPU_ARCH_MIPS32	(1 << 5)
    177 #define	CPU_ARCH_MIPS64	(1 << 6)
    178 
    179 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */
    180 #define MIPS_CURLWP             $24
    181 #define MIPS_CURLWP_QUOTED      "$24"
    182 #define MIPS_CURLWP_LABEL	_L_T8
    183 #define MIPS_CURLWP_REG		_R_T8
    184 #define TF_MIPS_CURLWP(x)	TF_REG_T8(x)
    185 
    186 #ifndef _LOCORE
    187 
    188 extern struct cpu_info cpu_info_store;
    189 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED);
    190 
    191 #define	curlwp			mips_curlwp
    192 #define	curcpu()		(curlwp->l_cpu)
    193 #define	curpcb			(&curlwp->l_addr->u_pcb)
    194 #ifdef MULTIPROCESSOR
    195 #define	cpu_number()		(curcpu()->ci_cpuid)
    196 #define	CPU_IS_PRIMARY(ci)	((ci)->ci_cpuid == 0)
    197 #else
    198 #define	cpu_number()		(0L)
    199 #endif
    200 #define	cpu_proc_fork(p1, p2)	((void)((p2)->p_md.md_abi = (p1)->p_md.md_abi))
    201 
    202 /* XXX simonb
    203  * Should the following be in a cpu_info type structure?
    204  * And how many of these are per-cpu vs. per-system?  (Ie,
    205  * we can assume that all cpus have the same mmu-type, but
    206  * maybe not that all cpus run at the same clock speed.
    207  * Some SGI's apparently support R12k and R14k in the same
    208  * box.)
    209  */
    210 struct mips_options {
    211 	const struct pridtab *mips_cpu;
    212 
    213 	u_int mips_cpu_arch;
    214 	u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */
    215 	u_int mips_cpu_flags;
    216 	u_int mips_num_tlb_entries;
    217 	mips_prid_t mips_cpu_id;
    218 	mips_prid_t mips_fpu_id;
    219 	bool mips_has_r4k_mmu;
    220 	bool mips_has_llsc;
    221 	u_int mips3_pg_shift;
    222 	u_int mips3_pg_cached;
    223 #ifdef MIPS3_PLUS
    224 #ifdef _LP64
    225 	uint64_t mips3_xkphys_cached;
    226 #endif
    227 	uint64_t mips3_tlb_vpn_mask;
    228 	uint64_t mips3_tlb_pfn_mask;
    229 	uint32_t mips3_tlb_pg_mask;
    230 #endif
    231 };
    232 extern struct mips_options mips_options;
    233 
    234 #define	CPU_MIPS_R4K_MMU		0x0001
    235 #define	CPU_MIPS_NO_LLSC		0x0002
    236 #define	CPU_MIPS_CAUSE_IV		0x0004
    237 #define	CPU_MIPS_HAVE_SPECIAL_CCA	0x0008	/* Defaults to '3' if not set. */
    238 #define	CPU_MIPS_CACHED_CCA_MASK	0x0070
    239 #define	CPU_MIPS_CACHED_CCA_SHIFT	 4
    240 #define	CPU_MIPS_DOUBLE_COUNT		0x0080	/* 1 cp0 count == 2 clock cycles */
    241 #define	CPU_MIPS_USE_WAIT		0x0100	/* Use "wait"-based cpu_idle() */
    242 #define	CPU_MIPS_NO_WAIT		0x0200	/* Inverse of previous, for mips32/64 */
    243 #define	CPU_MIPS_D_CACHE_COHERENT	0x0400	/* D-cache is fully coherent */
    244 #define	CPU_MIPS_I_D_CACHE_COHERENT	0x0800	/* I-cache funcs don't need to flush the D-cache */
    245 #define	CPU_MIPS_NO_LLADDR		0x1000
    246 #define	CPU_MIPS_HAVE_MxCR		0x2000	/* have mfcr, mtcr insns */
    247 #define	MIPS_NOT_SUPP			0x8000
    248 
    249 #endif	/* !_LOCORE */
    250 
    251 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE)
    252 
    253 #if defined(MIPS1)
    254 
    255 # define CPUISMIPS3		0
    256 # define CPUIS64BITS		0
    257 # define CPUISMIPS32		0
    258 # define CPUISMIPS64		0
    259 # define CPUISMIPSNN		0
    260 # define MIPS_HAS_R4K_MMU	0
    261 # define MIPS_HAS_CLOCK		0
    262 # define MIPS_HAS_LLSC		0
    263 # define MIPS_HAS_LLADDR	0
    264 
    265 #elif defined(MIPS3) || defined(MIPS4)
    266 
    267 # define CPUISMIPS3		1
    268 # define CPUIS64BITS		1
    269 # define CPUISMIPS32		0
    270 # define CPUISMIPS64		0
    271 # define CPUISMIPSNN		0
    272 # define MIPS_HAS_R4K_MMU	1
    273 # define MIPS_HAS_CLOCK		1
    274 # if defined(_LOCORE)
    275 #  if !defined(MIPS3_5900) && !defined(MIPS3_4100)
    276 #   define MIPS_HAS_LLSC	1
    277 #  else
    278 #   define MIPS_HAS_LLSC	0
    279 #  endif
    280 # else	/* _LOCORE */
    281 #  define MIPS_HAS_LLSC		(mips_options.mips_has_llsc)
    282 # endif	/* _LOCORE */
    283 # define MIPS_HAS_LLADDR	((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
    284 
    285 #elif defined(MIPS32)
    286 
    287 # define CPUISMIPS3		1
    288 # define CPUIS64BITS		0
    289 # define CPUISMIPS32		1
    290 # define CPUISMIPS64		0
    291 # define CPUISMIPSNN		1
    292 # define MIPS_HAS_R4K_MMU	1
    293 # define MIPS_HAS_CLOCK		1
    294 # define MIPS_HAS_LLSC		1
    295 # define MIPS_HAS_LLADDR	((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
    296 
    297 #elif defined(MIPS64)
    298 
    299 # define CPUISMIPS3		1
    300 # define CPUIS64BITS		1
    301 # define CPUISMIPS32		0
    302 # define CPUISMIPS64		1
    303 # define CPUISMIPSNN		1
    304 # define MIPS_HAS_R4K_MMU	1
    305 # define MIPS_HAS_CLOCK		1
    306 # define MIPS_HAS_LLSC		1
    307 # define MIPS_HAS_LLADDR	((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
    308 
    309 #endif
    310 
    311 #else /* run-time test */
    312 
    313 #ifndef	_LOCORE
    314 
    315 #define	MIPS_HAS_R4K_MMU	(mips_options.mips_has_r4k_mmu)
    316 #define	MIPS_HAS_LLSC		(mips_options.mips_has_llsc)
    317 #define	MIPS_HAS_LLADDR		((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
    318 
    319 /* This test is ... rather bogus */
    320 #define	CPUISMIPS3	((mips_options.mips_cpu_arch & \
    321 	(CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0)
    322 
    323 /* And these aren't much better while the previous test exists as is... */
    324 #define	CPUISMIPS4	((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0)
    325 #define	CPUISMIPS5	((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0)
    326 #define	CPUISMIPS32	((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0)
    327 #define	CPUISMIPS64	((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0)
    328 #define	CPUISMIPSNN	((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0)
    329 #define	CPUIS64BITS	((mips_options.mips_cpu_arch & \
    330 	(CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0)
    331 
    332 #define	MIPS_HAS_CLOCK	(mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3)
    333 
    334 #else	/* !_LOCORE */
    335 
    336 #define	MIPS_HAS_LLSC	0
    337 
    338 #endif	/* !_LOCORE */
    339 
    340 #endif /* run-time test */
    341 
    342 #ifndef	_LOCORE
    343 
    344 /*
    345  * definitions of cpu-dependent requirements
    346  * referenced in generic code
    347  */
    348 #define	cpu_swapout(p)			panic("cpu_swapout: can't get here");
    349 
    350 /*
    351  * Send an inter-processor interupt to another CPU.
    352  */
    353 int cpu_send_ipi(struct cpu_info *, int);
    354 
    355 /*
    356  * cpu_intr(ppl, pc, status);  (most state needed by clockframe)
    357  */
    358 void cpu_intr(int, vaddr_t, uint32_t);
    359 
    360 /*
    361  * Arguments to hardclock and gatherstats encapsulate the previous
    362  * machine state in an opaque clockframe.
    363  */
    364 struct clockframe {
    365 	vaddr_t		pc;	/* program counter at time of interrupt */
    366 	uint32_t	sr;	/* status register at time of interrupt */
    367 	bool		intr;	/* interrupted a interrupt */
    368 };
    369 
    370 /*
    371  * A port must provde CLKF_USERMODE() for use in machine-independent code.
    372  * These differ on r4000 and r3000 systems; provide them in the
    373  * port-dependent file that includes this one, using the macros below.
    374  */
    375 
    376 /* mips1 versions */
    377 #define	MIPS1_CLKF_USERMODE(framep)	((framep)->sr & MIPS_SR_KU_PREV)
    378 
    379 /* mips3 versions */
    380 #define	MIPS3_CLKF_USERMODE(framep)	((framep)->sr & MIPS_SR_KSU_USER)
    381 
    382 #define	CLKF_PC(framep)		((framep)->pc)
    383 #define	CLKF_INTR(framep)	((framep)->intr)
    384 
    385 #if defined(MIPS3_PLUS) && !defined(MIPS1)		/* XXX bogus! */
    386 #define	CLKF_USERMODE(framep)	MIPS3_CLKF_USERMODE(framep)
    387 #endif
    388 
    389 #if !defined(MIPS3_PLUS) && defined(MIPS1)		/* XXX bogus! */
    390 #define	CLKF_USERMODE(framep)	MIPS1_CLKF_USERMODE(framep)
    391 #endif
    392 
    393 #if defined(MIPS3_PLUS) && defined(MIPS1)		/* XXX bogus! */
    394 #define CLKF_USERMODE(framep) \
    395     ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep):  MIPS1_CLKF_USERMODE(framep))
    396 #endif
    397 
    398 /*
    399  * Misc prototypes and variable declarations.
    400  */
    401 struct lwp;
    402 struct user;
    403 
    404 /*
    405  * Preempt the current process if in interrupt from user mode,
    406  * or after the current trap/syscall if in system mode.
    407  */
    408 void	cpu_need_resched(struct cpu_info *, int);
    409 /*
    410  * Notify the current lwp (l) that it has a signal pending,
    411  * process as soon as possible.
    412  */
    413 void	cpu_signotify(struct lwp *);
    414 
    415 /*
    416  * Give a profiling tick to the current process when the user profiling
    417  * buffer pages are invalid.  On the MIPS, request an ast to send us
    418  * through trap, marking the proc as needing a profiling tick.
    419  */
    420 void	cpu_need_proftick(struct lwp *);
    421 void	cpu_set_curpri(int);
    422 
    423 extern int mips_poolpage_vmfreelist;	/* freelist to allocate poolpages */
    424 
    425 /* cpu_subr.c */
    426 #ifdef MULTIPROCESSOR
    427 extern volatile u_long cpus_running;
    428 extern volatile u_long cpus_hatched;
    429 extern volatile u_long cpus_halted;
    430 #endif
    431 
    432 struct cpu_info *
    433 	cpu_info_alloc(struct pmap_tlb_info *, u_int);
    434 void	cpu_attach_common(device_t, struct cpu_info *);
    435 void	cpu_startup_common(void);
    436 #ifdef MULTIPROCESSOR
    437 void	cpu_hatch(struct cpu_info *ci);
    438 void	cpu_trampoline(void);
    439 void	cpu_boot_secondary_processors(void);
    440 #endif
    441 
    442 /* copy.S */
    443 int8_t	ufetch_int8(void *);
    444 int16_t	ufetch_int16(void *);
    445 int32_t ufetch_int32(void *);
    446 uint8_t	ufetch_uint8(void *);
    447 uint16_t ufetch_uint16(void *);
    448 uint32_t ufetch_uint32(void *);
    449 int8_t	ufetch_int8_intrsafe(void *);
    450 int16_t	ufetch_int16_intrsafe(void *);
    451 int32_t ufetch_int32_intrsafe(void *);
    452 uint8_t	ufetch_uint8_intrsafe(void *);
    453 uint16_t ufetch_uint16_intrsafe(void *);
    454 uint32_t ufetch_uint32_intrsafe(void *);
    455 #ifdef _LP64
    456 int64_t ufetch_int64(void *);
    457 uint64_t ufetch_uint64(void *);
    458 int64_t ufetch_int64_intrsafe(void *);
    459 uint64_t ufetch_uint64_intrsafe(void *);
    460 #endif
    461 char	ufetch_char(void *);
    462 short	ufetch_short(void *);
    463 int	ufetch_int(void *);
    464 long	ufetch_long(void *);
    465 char	ufetch_char_intrsafe(void *);
    466 short	ufetch_short_intrsafe(void *);
    467 int	ufetch_int_intrsafe(void *);
    468 long	ufetch_long_intrsafe(void *);
    469 
    470 u_char	ufetch_uchar(void *);
    471 u_short	ufetch_ushort(void *);
    472 u_int	ufetch_uint(void *);
    473 u_long	ufetch_ulong(void *);
    474 u_char	ufetch_uchar_intrsafe(void *);
    475 u_short	ufetch_ushort_intrsafe(void *);
    476 u_int	ufetch_uint_intrsafe(void *);
    477 u_long	ufetch_ulong_intrsafe(void *);
    478 void 	*ufetch_ptr(void *);
    479 
    480 int	ustore_int8(void *, int8_t);
    481 int	ustore_int16(void *, int16_t);
    482 int	ustore_int32(void *, int32_t);
    483 int	ustore_uint8(void *, uint8_t);
    484 int	ustore_uint16(void *, uint16_t);
    485 int	ustore_uint32(void *, uint32_t);
    486 int	ustore_int8_intrsafe(void *, int8_t);
    487 int	ustore_int16_intrsafe(void *, int16_t);
    488 int	ustore_int32_intrsafe(void *, int32_t);
    489 int	ustore_uint8_intrsafe(void *, uint8_t);
    490 int	ustore_uint16_intrsafe(void *, uint16_t);
    491 int	ustore_uint32_intrsafe(void *, uint32_t);
    492 #ifdef _LP64
    493 int	ustore_int64(void *, int64_t);
    494 int	ustore_uint64(void *, uint64_t);
    495 int	ustore_int64_intrsafe(void *, int64_t);
    496 int	ustore_uint64_intrsafe(void *, uint64_t);
    497 #endif
    498 int	ustore_char(void *, char);
    499 int	ustore_char_intrsafe(void *, char);
    500 int	ustore_short(void *, short);
    501 int	ustore_short_intrsafe(void *, short);
    502 int	ustore_int(void *, int);
    503 int	ustore_int_intrsafe(void *, int);
    504 int	ustore_long(void *, long);
    505 int	ustore_long_intrsafe(void *, long);
    506 int	ustore_uchar(void *, u_char);
    507 int	ustore_uchar_intrsafe(void *, u_char);
    508 int	ustore_ushort(void *, u_short);
    509 int	ustore_ushort_intrsafe(void *, u_short);
    510 int	ustore_uint(void *, u_int);
    511 int	ustore_uint_intrsafe(void *, u_int);
    512 int	ustore_ulong(void *, u_long);
    513 int	ustore_ulong_intrsafe(void *, u_long);
    514 int 	ustore_ptr(void *, void *);
    515 int	ustore_ptr_intrsafe(void *, void *);
    516 
    517 int	ustore_uint32_isync(void *, uint32_t);
    518 
    519 /* trap.c */
    520 void	netintr(void);
    521 int	kdbpeek(vaddr_t);
    522 
    523 /* mips_fpu.c */
    524 void	fpu_init(void);
    525 void	fpudiscard_lwp(struct lwp *);
    526 void	fpuload_lwp(struct lwp *);
    527 void	fpusave_lwp(struct lwp *);
    528 void	fpusave_cpu(struct cpu_info *);
    529 
    530 /* mips_machdep.c */
    531 struct mips_vmfreelist;
    532 struct phys_ram_seg;
    533 void	dumpsys(void);
    534 int	savectx(struct user *);
    535 void	mips_init_msgbuf(void);
    536 void	mips_init_lwp0_uarea(void);
    537 void	mips_page_physload(vaddr_t, vaddr_t,
    538 	    const struct phys_ram_seg *, size_t,
    539 	    const struct mips_vmfreelist *, size_t);
    540 void	cpu_identify(device_t);
    541 
    542 /* locore*.S */
    543 int	badaddr(void *, size_t);
    544 int	badaddr64(uint64_t, size_t);
    545 
    546 /* vm_machdep.c */
    547 void	cpu_uarea_remap(struct lwp *);
    548 
    549 #endif /* ! _LOCORE */
    550 #endif /* _KERNEL */
    551 #endif /* _CPU_H_ */
    552