cpu.h revision 1.90.16.29
1 /* $NetBSD: cpu.h,v 1.90.16.29 2010/06/09 14:20:00 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 48 #ifndef _LOCORE 49 #include <sys/cpu_data.h> 50 #include <sys/device.h> 51 #include <sys/evcnt.h> 52 53 #if defined(_KERNEL_OPT) 54 #include "opt_cputype.h" 55 #include "opt_lockdebug.h" 56 #include "opt_multiprocessor.h" 57 #endif 58 59 struct cpu_info { 60 struct cpu_data ci_data; /* MI per-cpu data */ 61 struct cpu_info *ci_next; /* Next CPU in list */ 62 struct cpu_softc *ci_softc; /* chip-dependent hook */ 63 device_t ci_dev; /* owning device */ 64 cpuid_t ci_cpuid; /* Machine-level identifier */ 65 u_long ci_cctr_freq; /* cycle counter frequency */ 66 u_long ci_cpu_freq; /* CPU frequency */ 67 u_long ci_cycles_per_hz; /* CPU freq / hz */ 68 u_long ci_divisor_delay; /* for delay/DELAY */ 69 u_long ci_divisor_recip; /* unused, for obsolete microtime(9) */ 70 struct lwp *ci_curlwp; /* currently running lwp */ 71 #ifndef NOFPU 72 struct lwp *ci_fpcurlwp; /* the current FPU owner */ 73 #endif 74 volatile int ci_want_resched; /* user preemption pending */ 75 int ci_mtx_count; /* negative count of held mutexes */ 76 int ci_mtx_oldspl; /* saved SPL value */ 77 int ci_idepth; /* hardware interrupt depth */ 78 int ci_cpl; /* current [interrupt] priority level */ 79 uint32_t ci_next_cp0_clk_intr; /* for hard clock intr scheduling */ 80 struct evcnt ci_count_compare_evcnt; /* hard clock intr counter */ 81 struct evcnt ci_count_compare_missed_evcnt; /* hard clock miss counter */ 82 struct lwp *ci_softlwps[SOFTINT_COUNT]; 83 #define ci_softints ci_data.cpu_softints 84 85 /* 86 * Per-cpu pmap information 87 */ 88 int ci_tlb_slot; /* reserved tlb entry for cpu_info */ 89 struct pmap_tlb_info *ci_tlb_info; /* tlb information for this cpu */ 90 struct segtab *ci_pmap_segbase; 91 vaddr_t ci_pmap_srcbase; /* starting VA of ephemeral src space */ 92 vaddr_t ci_pmap_dstbase; /* starting VA of ephemeral dst space */ 93 94 95 #ifdef MULTIPROCESSOR 96 volatile u_long ci_flags; 97 volatile uint64_t ci_request_ipis; 98 /* bitmask of IPIs requested */ 99 /* use on chips where hw cannot pass tag */ 100 uint64_t ci_active_ipis; /* bitmask of IPIs being serviced */ 101 uint32_t ci_ksp_tlb_slot; /* tlb entry for kernel stack */ 102 void *ci_fpsave_si; /* FP sync softint handler */ 103 struct evcnt ci_evcnt_all_ipis; /* aggregated IPI counter */ 104 struct evcnt ci_evcnt_per_ipi[NIPIS]; /* individual IPI counters*/ 105 struct evcnt ci_evcnt_synci_activate_rqst; 106 struct evcnt ci_evcnt_synci_onproc_rqst; 107 struct evcnt ci_evcnt_synci_deferred_rqst; 108 struct evcnt ci_evcnt_synci_ipi_rqst; 109 110 #define CPUF_PRIMARY 0x01 /* CPU is primary CPU */ 111 #define CPUF_PRESENT 0x02 /* CPU is present */ 112 #define CPUF_RUNNING 0x04 /* CPU is running */ 113 #define CPUF_PAUSED 0x08 /* CPU is paused */ 114 #define CPUF_FPUSAVE 0x10 /* CPU is currently in fpusave_cpu() */ 115 #define CPUF_USERPMAP 0x20 /* CPU has a user pmap activated */ 116 #endif 117 118 }; 119 120 #define CPU_INFO_ITERATOR int 121 #define CPU_INFO_FOREACH(cii, ci) \ 122 (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next 123 124 #endif /* !_LOCORE */ 125 #endif /* _KERNEL */ 126 127 /* 128 * CTL_MACHDEP definitions. 129 */ 130 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 131 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 132 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 133 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 134 135 /* 136 * Platform can override, but note this breaks userland compatibility 137 * with other mips platforms. 138 */ 139 #ifndef CPU_MAXID 140 #define CPU_MAXID 5 /* number of valid machdep ids */ 141 #endif 142 143 #ifdef _KERNEL 144 #if defined(_LKM) || defined(_STANDALONE) 145 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 146 #define MIPS1 1 147 #define MIPS3 1 148 #define MIPS4 1 149 #define MIPS32 1 150 #define MIPS64 1 151 #endif 152 153 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 154 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 155 #endif 156 157 /* Shortcut for MIPS3 or above defined */ 158 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 159 #define MIPS3_PLUS 1 160 #define __HAVE_CPU_COUNTER 161 #else 162 #undef MIPS3_PLUS 163 #endif 164 165 /* 166 * Macros to find the CPU architecture we're on at run-time, 167 * or if possible, at compile-time. 168 */ 169 170 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 171 #define CPU_ARCH_MIPS1 (1 << 0) 172 #define CPU_ARCH_MIPS2 (1 << 1) 173 #define CPU_ARCH_MIPS3 (1 << 2) 174 #define CPU_ARCH_MIPS4 (1 << 3) 175 #define CPU_ARCH_MIPS5 (1 << 4) 176 #define CPU_ARCH_MIPS32 (1 << 5) 177 #define CPU_ARCH_MIPS64 (1 << 6) 178 179 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 180 #define MIPS_CURLWP $24 181 #define MIPS_CURLWP_QUOTED "$24" 182 #define MIPS_CURLWP_LABEL _L_T8 183 #define MIPS_CURLWP_REG _R_T8 184 #define TF_MIPS_CURLWP(x) TF_REG_T8(x) 185 186 #ifndef _LOCORE 187 188 extern struct cpu_info cpu_info_store; 189 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 190 191 #define curlwp mips_curlwp 192 #define curcpu() (curlwp->l_cpu) 193 #define curpcb (&curlwp->l_addr->u_pcb) 194 #ifdef MULTIPROCESSOR 195 #define cpu_number() (curcpu()->ci_cpuid) 196 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 197 #else 198 #define cpu_number() (0L) 199 #endif 200 201 /* XXX simonb 202 * Should the following be in a cpu_info type structure? 203 * And how many of these are per-cpu vs. per-system? (Ie, 204 * we can assume that all cpus have the same mmu-type, but 205 * maybe not that all cpus run at the same clock speed. 206 * Some SGI's apparently support R12k and R14k in the same 207 * box.) 208 */ 209 struct mips_options { 210 const struct pridtab *mips_cpu; 211 212 u_int mips_cpu_arch; 213 u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */ 214 u_int mips_cpu_flags; 215 u_int mips_num_tlb_entries; 216 mips_prid_t mips_cpu_id; 217 mips_prid_t mips_fpu_id; 218 bool mips_has_r4k_mmu; 219 bool mips_has_llsc; 220 u_int mips3_pg_shift; 221 u_int mips3_pg_cached; 222 #ifdef MIPS3_PLUS 223 #ifdef _LP64 224 uint64_t mips3_xkphys_cached; 225 #endif 226 uint64_t mips3_tlb_vpn_mask; 227 uint64_t mips3_tlb_pfn_mask; 228 uint32_t mips3_tlb_pg_mask; 229 #endif 230 }; 231 extern struct mips_options mips_options; 232 233 #define CPU_MIPS_R4K_MMU 0x0001 234 #define CPU_MIPS_NO_LLSC 0x0002 235 #define CPU_MIPS_CAUSE_IV 0x0004 236 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 237 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 238 #define CPU_MIPS_CACHED_CCA_SHIFT 4 239 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 240 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 241 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 242 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 243 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 244 #define CPU_MIPS_NO_LLADDR 0x1000 245 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 246 #define MIPS_NOT_SUPP 0x8000 247 248 #endif /* !_LOCORE */ 249 250 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE) 251 252 #if defined(MIPS1) 253 254 # define CPUISMIPS3 0 255 # define CPUIS64BITS 0 256 # define CPUISMIPS32 0 257 # define CPUISMIPS64 0 258 # define CPUISMIPSNN 0 259 # define MIPS_HAS_R4K_MMU 0 260 # define MIPS_HAS_CLOCK 0 261 # define MIPS_HAS_LLSC 0 262 # define MIPS_HAS_LLADDR 0 263 264 #elif defined(MIPS3) || defined(MIPS4) 265 266 # define CPUISMIPS3 1 267 # define CPUIS64BITS 1 268 # define CPUISMIPS32 0 269 # define CPUISMIPS64 0 270 # define CPUISMIPSNN 0 271 # define MIPS_HAS_R4K_MMU 1 272 # define MIPS_HAS_CLOCK 1 273 # if defined(_LOCORE) 274 # if !defined(MIPS3_5900) && !defined(MIPS3_4100) 275 # define MIPS_HAS_LLSC 1 276 # else 277 # define MIPS_HAS_LLSC 0 278 # endif 279 # else /* _LOCORE */ 280 # define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 281 # endif /* _LOCORE */ 282 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 283 284 #elif defined(MIPS32) 285 286 # define CPUISMIPS3 1 287 # define CPUIS64BITS 0 288 # define CPUISMIPS32 1 289 # define CPUISMIPS64 0 290 # define CPUISMIPSNN 1 291 # define MIPS_HAS_R4K_MMU 1 292 # define MIPS_HAS_CLOCK 1 293 # define MIPS_HAS_LLSC 1 294 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 295 296 #elif defined(MIPS64) 297 298 # define CPUISMIPS3 1 299 # define CPUIS64BITS 1 300 # define CPUISMIPS32 0 301 # define CPUISMIPS64 1 302 # define CPUISMIPSNN 1 303 # define MIPS_HAS_R4K_MMU 1 304 # define MIPS_HAS_CLOCK 1 305 # define MIPS_HAS_LLSC 1 306 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 307 308 #endif 309 310 #else /* run-time test */ 311 312 #ifndef _LOCORE 313 314 #define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu) 315 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 316 #define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 317 318 /* This test is ... rather bogus */ 319 #define CPUISMIPS3 ((mips_options.mips_cpu_arch & \ 320 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 321 322 /* And these aren't much better while the previous test exists as is... */ 323 #define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0) 324 #define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0) 325 #define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0) 326 #define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0) 327 #define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 328 #define CPUIS64BITS ((mips_options.mips_cpu_arch & \ 329 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 330 331 #define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) 332 333 #else /* !_LOCORE */ 334 335 #define MIPS_HAS_LLSC 0 336 337 #endif /* !_LOCORE */ 338 339 #endif /* run-time test */ 340 341 #ifndef _LOCORE 342 343 /* 344 * definitions of cpu-dependent requirements 345 * referenced in generic code 346 */ 347 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 348 349 /* 350 * Send an inter-processor interupt to another CPU. 351 */ 352 int cpu_send_ipi(struct cpu_info *, int); 353 354 /* 355 * cpu_intr(ppl, pc, status); (most state needed by clockframe) 356 */ 357 void cpu_intr(int, vaddr_t, uint32_t); 358 359 /* 360 * Arguments to hardclock and gatherstats encapsulate the previous 361 * machine state in an opaque clockframe. 362 */ 363 struct clockframe { 364 vaddr_t pc; /* program counter at time of interrupt */ 365 uint32_t sr; /* status register at time of interrupt */ 366 bool intr; /* interrupted a interrupt */ 367 }; 368 369 /* 370 * A port must provde CLKF_USERMODE() for use in machine-independent code. 371 * These differ on r4000 and r3000 systems; provide them in the 372 * port-dependent file that includes this one, using the macros below. 373 */ 374 375 /* mips1 versions */ 376 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 377 378 /* mips3 versions */ 379 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 380 381 #define CLKF_PC(framep) ((framep)->pc) 382 #define CLKF_INTR(framep) ((framep)->intr) 383 384 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 385 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 386 #endif 387 388 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 389 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 390 #endif 391 392 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 393 #define CLKF_USERMODE(framep) \ 394 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 395 #endif 396 397 /* 398 * Misc prototypes and variable declarations. 399 */ 400 struct lwp; 401 struct user; 402 403 /* 404 * Preempt the current process if in interrupt from user mode, 405 * or after the current trap/syscall if in system mode. 406 */ 407 void cpu_need_resched(struct cpu_info *, int); 408 /* 409 * Notify the current lwp (l) that it has a signal pending, 410 * process as soon as possible. 411 */ 412 void cpu_signotify(struct lwp *); 413 414 /* 415 * Give a profiling tick to the current process when the user profiling 416 * buffer pages are invalid. On the MIPS, request an ast to send us 417 * through trap, marking the proc as needing a profiling tick. 418 */ 419 void cpu_need_proftick(struct lwp *); 420 void cpu_set_curpri(int); 421 422 extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */ 423 424 /* cpu_subr.c */ 425 #ifdef MULTIPROCESSOR 426 extern volatile u_long cpus_running; 427 extern volatile u_long cpus_hatched; 428 extern volatile u_long cpus_halted; 429 #endif 430 431 struct cpu_info * 432 cpu_info_alloc(struct pmap_tlb_info *, u_int); 433 void cpu_attach_common(device_t, struct cpu_info *); 434 void cpu_startup_common(void); 435 #ifdef MULTIPROCESSOR 436 void cpu_hatch(struct cpu_info *ci); 437 void cpu_trampoline(void); 438 void cpu_boot_secondary_processors(void); 439 #endif 440 441 /* copy.S */ 442 int8_t ufetch_int8(void *); 443 int16_t ufetch_int16(void *); 444 int32_t ufetch_int32(void *); 445 uint8_t ufetch_uint8(void *); 446 uint16_t ufetch_uint16(void *); 447 uint32_t ufetch_uint32(void *); 448 int8_t ufetch_int8_intrsafe(void *); 449 int16_t ufetch_int16_intrsafe(void *); 450 int32_t ufetch_int32_intrsafe(void *); 451 uint8_t ufetch_uint8_intrsafe(void *); 452 uint16_t ufetch_uint16_intrsafe(void *); 453 uint32_t ufetch_uint32_intrsafe(void *); 454 #ifdef _LP64 455 int64_t ufetch_int64(void *); 456 uint64_t ufetch_uint64(void *); 457 int64_t ufetch_int64_intrsafe(void *); 458 uint64_t ufetch_uint64_intrsafe(void *); 459 #endif 460 char ufetch_char(void *); 461 short ufetch_short(void *); 462 int ufetch_int(void *); 463 long ufetch_long(void *); 464 char ufetch_char_intrsafe(void *); 465 short ufetch_short_intrsafe(void *); 466 int ufetch_int_intrsafe(void *); 467 long ufetch_long_intrsafe(void *); 468 469 u_char ufetch_uchar(void *); 470 u_short ufetch_ushort(void *); 471 u_int ufetch_uint(void *); 472 u_long ufetch_ulong(void *); 473 u_char ufetch_uchar_intrsafe(void *); 474 u_short ufetch_ushort_intrsafe(void *); 475 u_int ufetch_uint_intrsafe(void *); 476 u_long ufetch_ulong_intrsafe(void *); 477 void *ufetch_ptr(void *); 478 479 int ustore_int8(void *, int8_t); 480 int ustore_int16(void *, int16_t); 481 int ustore_int32(void *, int32_t); 482 int ustore_uint8(void *, uint8_t); 483 int ustore_uint16(void *, uint16_t); 484 int ustore_uint32(void *, uint32_t); 485 int ustore_int8_intrsafe(void *, int8_t); 486 int ustore_int16_intrsafe(void *, int16_t); 487 int ustore_int32_intrsafe(void *, int32_t); 488 int ustore_uint8_intrsafe(void *, uint8_t); 489 int ustore_uint16_intrsafe(void *, uint16_t); 490 int ustore_uint32_intrsafe(void *, uint32_t); 491 #ifdef _LP64 492 int ustore_int64(void *, int64_t); 493 int ustore_uint64(void *, uint64_t); 494 int ustore_int64_intrsafe(void *, int64_t); 495 int ustore_uint64_intrsafe(void *, uint64_t); 496 #endif 497 int ustore_char(void *, char); 498 int ustore_char_intrsafe(void *, char); 499 int ustore_short(void *, short); 500 int ustore_short_intrsafe(void *, short); 501 int ustore_int(void *, int); 502 int ustore_int_intrsafe(void *, int); 503 int ustore_long(void *, long); 504 int ustore_long_intrsafe(void *, long); 505 int ustore_uchar(void *, u_char); 506 int ustore_uchar_intrsafe(void *, u_char); 507 int ustore_ushort(void *, u_short); 508 int ustore_ushort_intrsafe(void *, u_short); 509 int ustore_uint(void *, u_int); 510 int ustore_uint_intrsafe(void *, u_int); 511 int ustore_ulong(void *, u_long); 512 int ustore_ulong_intrsafe(void *, u_long); 513 int ustore_ptr(void *, void *); 514 int ustore_ptr_intrsafe(void *, void *); 515 516 int ustore_uint32_isync(void *, uint32_t); 517 518 /* trap.c */ 519 void netintr(void); 520 int kdbpeek(vaddr_t); 521 522 /* mips_fpu.c */ 523 void fpu_init(void); 524 void fpudiscard_lwp(struct lwp *); 525 void fpuload_lwp(struct lwp *); 526 void fpusave_lwp(struct lwp *); 527 void fpusave_cpu(struct cpu_info *); 528 529 /* mips_machdep.c */ 530 struct mips_vmfreelist; 531 struct phys_ram_seg; 532 void dumpsys(void); 533 int savectx(struct user *); 534 void mips_init_msgbuf(void); 535 void mips_init_lwp0_uarea(void); 536 void mips_page_physload(vaddr_t, vaddr_t, 537 const struct phys_ram_seg *, size_t, 538 const struct mips_vmfreelist *, size_t); 539 void cpu_identify(device_t); 540 541 /* locore*.S */ 542 int badaddr(void *, size_t); 543 int badaddr64(uint64_t, size_t); 544 545 /* vm_machdep.c */ 546 void cpu_uarea_remap(struct lwp *); 547 548 #endif /* ! _LOCORE */ 549 #endif /* _KERNEL */ 550 #endif /* _CPU_H_ */ 551
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