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cpu.h revision 1.90.16.31
      1 /*	$NetBSD: cpu.h,v 1.90.16.31 2010/08/18 17:01:20 matt Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1992, 1993
      5  *	The Regents of the University of California.  All rights reserved.
      6  *
      7  * This code is derived from software contributed to Berkeley by
      8  * Ralph Campbell and Rick Macklem.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. Neither the name of the University nor the names of its contributors
     19  *    may be used to endorse or promote products derived from this software
     20  *    without specific prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  * SUCH DAMAGE.
     33  *
     34  *	@(#)cpu.h	8.4 (Berkeley) 1/4/94
     35  */
     36 
     37 #ifndef _CPU_H_
     38 #define _CPU_H_
     39 
     40 #include <mips/cpuregs.h>
     41 
     42 /*
     43  * Exported definitions unique to NetBSD/mips cpu support.
     44  */
     45 
     46 #ifdef _KERNEL
     47 
     48 #ifndef _LOCORE
     49 #include <sys/cpu_data.h>
     50 #include <sys/device.h>
     51 #include <sys/evcnt.h>
     52 
     53 #if defined(_KERNEL_OPT)
     54 #include "opt_cputype.h"
     55 #include "opt_lockdebug.h"
     56 #include "opt_multiprocessor.h"
     57 #endif
     58 
     59 struct cpu_info {
     60 	struct cpu_data ci_data;	/* MI per-cpu data */
     61 	struct cpu_info *ci_next;	/* Next CPU in list */
     62 	struct cpu_softc *ci_softc;	/* chip-dependent hook */
     63 	device_t ci_dev;		/* owning device */
     64 	cpuid_t ci_cpuid;		/* Machine-level identifier */
     65 	u_long ci_cctr_freq;		/* cycle counter frequency */
     66 	u_long ci_cpu_freq;		/* CPU frequency */
     67 	u_long ci_cycles_per_hz;	/* CPU freq / hz */
     68 	u_long ci_divisor_delay;	/* for delay/DELAY */
     69 	u_long ci_divisor_recip;	/* unused, for obsolete microtime(9) */
     70 	struct lwp *ci_curlwp;		/* currently running lwp */
     71 #ifndef NOFPU
     72 	struct lwp *ci_fpcurlwp;	/* the current FPU owner */
     73 #endif
     74 	volatile int ci_want_resched;	/* user preemption pending */
     75 	int ci_mtx_count;		/* negative count of held mutexes */
     76 	int ci_mtx_oldspl;		/* saved SPL value */
     77 	int ci_idepth;			/* hardware interrupt depth */
     78 	int ci_cpl;			/* current [interrupt] priority level */
     79 	uint32_t ci_next_cp0_clk_intr;	/* for hard clock intr scheduling */
     80 	struct evcnt ci_count_compare_evcnt;		/* hard clock intr counter */
     81 	struct evcnt ci_count_compare_missed_evcnt;	/* hard clock miss counter */
     82 	struct lwp *ci_softlwps[SOFTINT_COUNT];
     83 #define	ci_softints	ci_data.cpu_softints
     84 
     85 	/*
     86 	 * Per-cpu pmap information
     87 	 */
     88 	int ci_tlb_slot;		/* reserved tlb entry for cpu_info */
     89 	struct pmap_tlb_info *ci_tlb_info; /* tlb information for this cpu */
     90 	union segtab *ci_pmap_seg0tab;
     91 #ifdef _LP64
     92 	union segtab *ci_pmap_segtab;
     93 #else
     94 	vaddr_t ci_pmap_srcbase;	/* starting VA of ephemeral src space */
     95 	vaddr_t ci_pmap_dstbase;	/* starting VA of ephemeral dst space */
     96 #endif
     97 
     98 
     99 #ifdef MULTIPROCESSOR
    100 	volatile u_long ci_flags;
    101 	volatile uint64_t ci_request_ipis;
    102 					/* bitmask of IPIs requested */
    103 					/*  use on chips where hw cannot pass tag */
    104 	uint64_t ci_active_ipis;	/* bitmask of IPIs being serviced */
    105 	uint32_t ci_ksp_tlb_slot;	/* tlb entry for kernel stack */
    106 	void *ci_fpsave_si;		/* FP sync softint handler */
    107 	struct evcnt ci_evcnt_all_ipis;	/* aggregated IPI counter */
    108 	struct evcnt ci_evcnt_per_ipi[NIPIS];	/* individual IPI counters*/
    109 	struct evcnt ci_evcnt_synci_activate_rqst;
    110 	struct evcnt ci_evcnt_synci_onproc_rqst;
    111 	struct evcnt ci_evcnt_synci_deferred_rqst;
    112 	struct evcnt ci_evcnt_synci_ipi_rqst;
    113 
    114 #define	CPUF_PRIMARY	0x01		/* CPU is primary CPU */
    115 #define	CPUF_PRESENT	0x02		/* CPU is present */
    116 #define	CPUF_RUNNING	0x04		/* CPU is running */
    117 #define	CPUF_PAUSED	0x08		/* CPU is paused */
    118 #define	CPUF_FPUSAVE	0x10		/* CPU is currently in fpusave_cpu() */
    119 #define	CPUF_USERPMAP	0x20		/* CPU has a user pmap activated */
    120 #endif
    121 
    122 };
    123 
    124 #define	CPU_INFO_ITERATOR		int
    125 #define	CPU_INFO_FOREACH(cii, ci)	\
    126     (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next
    127 
    128 #endif /* !_LOCORE */
    129 #endif /* _KERNEL */
    130 
    131 /*
    132  * CTL_MACHDEP definitions.
    133  */
    134 #define CPU_CONSDEV		1	/* dev_t: console terminal device */
    135 #define CPU_BOOTED_KERNEL	2	/* string: booted kernel name */
    136 #define CPU_ROOT_DEVICE		3	/* string: root device name */
    137 #define CPU_LLSC		4	/* OS/CPU supports LL/SC instruction */
    138 
    139 /*
    140  * Platform can override, but note this breaks userland compatibility
    141  * with other mips platforms.
    142  */
    143 #ifndef CPU_MAXID
    144 #define CPU_MAXID		5	/* number of valid machdep ids */
    145 #endif
    146 
    147 #ifdef _KERNEL
    148 #if defined(_LKM) || defined(_STANDALONE)
    149 /* Assume all CPU architectures are valid for LKM's and standlone progs */
    150 #define	MIPS1	1
    151 #define	MIPS3	1
    152 #define	MIPS4	1
    153 #define	MIPS32	1
    154 #define	MIPS64	1
    155 #endif
    156 
    157 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0
    158 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified
    159 #endif
    160 
    161 /* Shortcut for MIPS3 or above defined */
    162 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)
    163 #define	MIPS3_PLUS	1
    164 #define __HAVE_CPU_COUNTER
    165 #else
    166 #undef MIPS3_PLUS
    167 #endif
    168 
    169 /*
    170  * Macros to find the CPU architecture we're on at run-time,
    171  * or if possible, at compile-time.
    172  */
    173 
    174 #define	CPU_ARCH_MIPSx	0		/* XXX unknown */
    175 #define	CPU_ARCH_MIPS1	(1 << 0)
    176 #define	CPU_ARCH_MIPS2	(1 << 1)
    177 #define	CPU_ARCH_MIPS3	(1 << 2)
    178 #define	CPU_ARCH_MIPS4	(1 << 3)
    179 #define	CPU_ARCH_MIPS5	(1 << 4)
    180 #define	CPU_ARCH_MIPS32	(1 << 5)
    181 #define	CPU_ARCH_MIPS64	(1 << 6)
    182 
    183 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */
    184 #define MIPS_CURLWP             $24
    185 #define MIPS_CURLWP_QUOTED      "$24"
    186 #define MIPS_CURLWP_LABEL	_L_T8
    187 #define MIPS_CURLWP_REG		_R_T8
    188 #define TF_MIPS_CURLWP(x)	TF_REG_T8(x)
    189 
    190 #ifndef _LOCORE
    191 
    192 extern struct cpu_info cpu_info_store;
    193 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED);
    194 
    195 #define	curlwp			mips_curlwp
    196 #define	curcpu()		(curlwp->l_cpu)
    197 #define	curpcb			(&curlwp->l_addr->u_pcb)
    198 #ifdef MULTIPROCESSOR
    199 #define	cpu_number()		(curcpu()->ci_cpuid)
    200 #define	CPU_IS_PRIMARY(ci)	((ci)->ci_cpuid == 0)
    201 #else
    202 #define	cpu_number()		(0L)
    203 #endif
    204 
    205 /* XXX simonb
    206  * Should the following be in a cpu_info type structure?
    207  * And how many of these are per-cpu vs. per-system?  (Ie,
    208  * we can assume that all cpus have the same mmu-type, but
    209  * maybe not that all cpus run at the same clock speed.
    210  * Some SGI's apparently support R12k and R14k in the same
    211  * box.)
    212  */
    213 struct mips_options {
    214 	const struct pridtab *mips_cpu;
    215 
    216 	u_int mips_cpu_arch;
    217 	u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */
    218 	u_int mips_cpu_flags;
    219 	u_int mips_num_tlb_entries;
    220 	mips_prid_t mips_cpu_id;
    221 	mips_prid_t mips_fpu_id;
    222 	bool mips_has_r4k_mmu;
    223 	bool mips_has_llsc;
    224 	u_int mips3_pg_shift;
    225 	u_int mips3_pg_cached;
    226 #ifdef MIPS3_PLUS
    227 #ifdef _LP64
    228 	uint64_t mips3_xkphys_cached;
    229 #endif
    230 	uint64_t mips3_tlb_vpn_mask;
    231 	uint64_t mips3_tlb_pfn_mask;
    232 	uint32_t mips3_tlb_pg_mask;
    233 #endif
    234 };
    235 extern struct mips_options mips_options;
    236 
    237 #define	CPU_MIPS_R4K_MMU		0x0001
    238 #define	CPU_MIPS_NO_LLSC		0x0002
    239 #define	CPU_MIPS_CAUSE_IV		0x0004
    240 #define	CPU_MIPS_HAVE_SPECIAL_CCA	0x0008	/* Defaults to '3' if not set. */
    241 #define	CPU_MIPS_CACHED_CCA_MASK	0x0070
    242 #define	CPU_MIPS_CACHED_CCA_SHIFT	 4
    243 #define	CPU_MIPS_DOUBLE_COUNT		0x0080	/* 1 cp0 count == 2 clock cycles */
    244 #define	CPU_MIPS_USE_WAIT		0x0100	/* Use "wait"-based cpu_idle() */
    245 #define	CPU_MIPS_NO_WAIT		0x0200	/* Inverse of previous, for mips32/64 */
    246 #define	CPU_MIPS_D_CACHE_COHERENT	0x0400	/* D-cache is fully coherent */
    247 #define	CPU_MIPS_I_D_CACHE_COHERENT	0x0800	/* I-cache funcs don't need to flush the D-cache */
    248 #define	CPU_MIPS_NO_LLADDR		0x1000
    249 #define	CPU_MIPS_HAVE_MxCR		0x2000	/* have mfcr, mtcr insns */
    250 #define	MIPS_NOT_SUPP			0x8000
    251 
    252 #endif	/* !_LOCORE */
    253 
    254 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE)
    255 
    256 #if defined(MIPS1)
    257 
    258 # define CPUISMIPS3		0
    259 # define CPUIS64BITS		0
    260 # define CPUISMIPS32		0
    261 # define CPUISMIPS64		0
    262 # define CPUISMIPSNN		0
    263 # define MIPS_HAS_R4K_MMU	0
    264 # define MIPS_HAS_CLOCK		0
    265 # define MIPS_HAS_LLSC		0
    266 # define MIPS_HAS_LLADDR	0
    267 
    268 #elif defined(MIPS3) || defined(MIPS4)
    269 
    270 # define CPUISMIPS3		1
    271 # define CPUIS64BITS		1
    272 # define CPUISMIPS32		0
    273 # define CPUISMIPS64		0
    274 # define CPUISMIPSNN		0
    275 # define MIPS_HAS_R4K_MMU	1
    276 # define MIPS_HAS_CLOCK		1
    277 # if defined(_LOCORE)
    278 #  if !defined(MIPS3_5900) && !defined(MIPS3_4100)
    279 #   define MIPS_HAS_LLSC	1
    280 #  else
    281 #   define MIPS_HAS_LLSC	0
    282 #  endif
    283 # else	/* _LOCORE */
    284 #  define MIPS_HAS_LLSC		(mips_options.mips_has_llsc)
    285 # endif	/* _LOCORE */
    286 # define MIPS_HAS_LLADDR	((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
    287 
    288 #elif defined(MIPS32)
    289 
    290 # define CPUISMIPS3		1
    291 # define CPUIS64BITS		0
    292 # define CPUISMIPS32		1
    293 # define CPUISMIPS64		0
    294 # define CPUISMIPSNN		1
    295 # define MIPS_HAS_R4K_MMU	1
    296 # define MIPS_HAS_CLOCK		1
    297 # define MIPS_HAS_LLSC		1
    298 # define MIPS_HAS_LLADDR	((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
    299 
    300 #elif defined(MIPS64)
    301 
    302 # define CPUISMIPS3		1
    303 # define CPUIS64BITS		1
    304 # define CPUISMIPS32		0
    305 # define CPUISMIPS64		1
    306 # define CPUISMIPSNN		1
    307 # define MIPS_HAS_R4K_MMU	1
    308 # define MIPS_HAS_CLOCK		1
    309 # define MIPS_HAS_LLSC		1
    310 # define MIPS_HAS_LLADDR	((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
    311 
    312 #endif
    313 
    314 #else /* run-time test */
    315 
    316 #ifndef	_LOCORE
    317 
    318 #define	MIPS_HAS_R4K_MMU	(mips_options.mips_has_r4k_mmu)
    319 #define	MIPS_HAS_LLSC		(mips_options.mips_has_llsc)
    320 #define	MIPS_HAS_LLADDR		((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
    321 
    322 /* This test is ... rather bogus */
    323 #define	CPUISMIPS3	((mips_options.mips_cpu_arch & \
    324 	(CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0)
    325 
    326 /* And these aren't much better while the previous test exists as is... */
    327 #define	CPUISMIPS4	((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0)
    328 #define	CPUISMIPS5	((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0)
    329 #define	CPUISMIPS32	((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0)
    330 #define	CPUISMIPS64	((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0)
    331 #define	CPUISMIPSNN	((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0)
    332 #define	CPUIS64BITS	((mips_options.mips_cpu_arch & \
    333 	(CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0)
    334 
    335 #define	MIPS_HAS_CLOCK	(mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3)
    336 
    337 #else	/* !_LOCORE */
    338 
    339 #define	MIPS_HAS_LLSC	0
    340 
    341 #endif	/* !_LOCORE */
    342 
    343 #endif /* run-time test */
    344 
    345 #ifndef	_LOCORE
    346 
    347 /*
    348  * definitions of cpu-dependent requirements
    349  * referenced in generic code
    350  */
    351 #define	cpu_swapout(p)			panic("cpu_swapout: can't get here");
    352 
    353 /*
    354  * Send an inter-processor interupt to another CPU.
    355  */
    356 int cpu_send_ipi(struct cpu_info *, int);
    357 
    358 /*
    359  * cpu_intr(ppl, pc, status);  (most state needed by clockframe)
    360  */
    361 void cpu_intr(int, vaddr_t, uint32_t);
    362 
    363 /*
    364  * Arguments to hardclock and gatherstats encapsulate the previous
    365  * machine state in an opaque clockframe.
    366  */
    367 struct clockframe {
    368 	vaddr_t		pc;	/* program counter at time of interrupt */
    369 	uint32_t	sr;	/* status register at time of interrupt */
    370 	bool		intr;	/* interrupted a interrupt */
    371 };
    372 
    373 /*
    374  * A port must provde CLKF_USERMODE() for use in machine-independent code.
    375  * These differ on r4000 and r3000 systems; provide them in the
    376  * port-dependent file that includes this one, using the macros below.
    377  */
    378 
    379 /* mips1 versions */
    380 #define	MIPS1_CLKF_USERMODE(framep)	((framep)->sr & MIPS_SR_KU_PREV)
    381 
    382 /* mips3 versions */
    383 #define	MIPS3_CLKF_USERMODE(framep)	((framep)->sr & MIPS_SR_KSU_USER)
    384 
    385 #define	CLKF_PC(framep)		((framep)->pc)
    386 #define	CLKF_INTR(framep)	((framep)->intr)
    387 
    388 #if defined(MIPS3_PLUS) && !defined(MIPS1)		/* XXX bogus! */
    389 #define	CLKF_USERMODE(framep)	MIPS3_CLKF_USERMODE(framep)
    390 #endif
    391 
    392 #if !defined(MIPS3_PLUS) && defined(MIPS1)		/* XXX bogus! */
    393 #define	CLKF_USERMODE(framep)	MIPS1_CLKF_USERMODE(framep)
    394 #endif
    395 
    396 #if defined(MIPS3_PLUS) && defined(MIPS1)		/* XXX bogus! */
    397 #define CLKF_USERMODE(framep) \
    398     ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep):  MIPS1_CLKF_USERMODE(framep))
    399 #endif
    400 
    401 /*
    402  * Misc prototypes and variable declarations.
    403  */
    404 struct lwp;
    405 struct user;
    406 
    407 /*
    408  * Preempt the current process if in interrupt from user mode,
    409  * or after the current trap/syscall if in system mode.
    410  */
    411 void	cpu_need_resched(struct cpu_info *, int);
    412 /*
    413  * Notify the current lwp (l) that it has a signal pending,
    414  * process as soon as possible.
    415  */
    416 void	cpu_signotify(struct lwp *);
    417 
    418 /*
    419  * Give a profiling tick to the current process when the user profiling
    420  * buffer pages are invalid.  On the MIPS, request an ast to send us
    421  * through trap, marking the proc as needing a profiling tick.
    422  */
    423 void	cpu_need_proftick(struct lwp *);
    424 void	cpu_set_curpri(int);
    425 
    426 extern int mips_poolpage_vmfreelist;	/* freelist to allocate poolpages */
    427 
    428 /* cpu_subr.c */
    429 #ifdef MULTIPROCESSOR
    430 extern volatile u_long cpus_running;
    431 extern volatile u_long cpus_hatched;
    432 extern volatile u_long cpus_halted;
    433 #endif
    434 
    435 struct cpu_info *
    436 	cpu_info_alloc(struct pmap_tlb_info *, u_int);
    437 void	cpu_attach_common(device_t, struct cpu_info *);
    438 void	cpu_startup_common(void);
    439 #ifdef _LP64
    440 void	cpu_vmspace_exec(struct lwp *, vaddr_t, vaddr_t);
    441 #endif
    442 #ifdef MULTIPROCESSOR
    443 void	cpu_hatch(struct cpu_info *ci);
    444 void	cpu_trampoline(void);
    445 void	cpu_boot_secondary_processors(void);
    446 #endif
    447 
    448 /* copy.S */
    449 int8_t	ufetch_int8(void *);
    450 int16_t	ufetch_int16(void *);
    451 int32_t ufetch_int32(void *);
    452 uint8_t	ufetch_uint8(void *);
    453 uint16_t ufetch_uint16(void *);
    454 uint32_t ufetch_uint32(void *);
    455 int8_t	ufetch_int8_intrsafe(void *);
    456 int16_t	ufetch_int16_intrsafe(void *);
    457 int32_t ufetch_int32_intrsafe(void *);
    458 uint8_t	ufetch_uint8_intrsafe(void *);
    459 uint16_t ufetch_uint16_intrsafe(void *);
    460 uint32_t ufetch_uint32_intrsafe(void *);
    461 #ifdef _LP64
    462 int64_t ufetch_int64(void *);
    463 uint64_t ufetch_uint64(void *);
    464 int64_t ufetch_int64_intrsafe(void *);
    465 uint64_t ufetch_uint64_intrsafe(void *);
    466 #endif
    467 char	ufetch_char(void *);
    468 short	ufetch_short(void *);
    469 int	ufetch_int(void *);
    470 long	ufetch_long(void *);
    471 char	ufetch_char_intrsafe(void *);
    472 short	ufetch_short_intrsafe(void *);
    473 int	ufetch_int_intrsafe(void *);
    474 long	ufetch_long_intrsafe(void *);
    475 
    476 u_char	ufetch_uchar(void *);
    477 u_short	ufetch_ushort(void *);
    478 u_int	ufetch_uint(void *);
    479 u_long	ufetch_ulong(void *);
    480 u_char	ufetch_uchar_intrsafe(void *);
    481 u_short	ufetch_ushort_intrsafe(void *);
    482 u_int	ufetch_uint_intrsafe(void *);
    483 u_long	ufetch_ulong_intrsafe(void *);
    484 void 	*ufetch_ptr(void *);
    485 
    486 int	ustore_int8(void *, int8_t);
    487 int	ustore_int16(void *, int16_t);
    488 int	ustore_int32(void *, int32_t);
    489 int	ustore_uint8(void *, uint8_t);
    490 int	ustore_uint16(void *, uint16_t);
    491 int	ustore_uint32(void *, uint32_t);
    492 int	ustore_int8_intrsafe(void *, int8_t);
    493 int	ustore_int16_intrsafe(void *, int16_t);
    494 int	ustore_int32_intrsafe(void *, int32_t);
    495 int	ustore_uint8_intrsafe(void *, uint8_t);
    496 int	ustore_uint16_intrsafe(void *, uint16_t);
    497 int	ustore_uint32_intrsafe(void *, uint32_t);
    498 #ifdef _LP64
    499 int	ustore_int64(void *, int64_t);
    500 int	ustore_uint64(void *, uint64_t);
    501 int	ustore_int64_intrsafe(void *, int64_t);
    502 int	ustore_uint64_intrsafe(void *, uint64_t);
    503 #endif
    504 int	ustore_char(void *, char);
    505 int	ustore_char_intrsafe(void *, char);
    506 int	ustore_short(void *, short);
    507 int	ustore_short_intrsafe(void *, short);
    508 int	ustore_int(void *, int);
    509 int	ustore_int_intrsafe(void *, int);
    510 int	ustore_long(void *, long);
    511 int	ustore_long_intrsafe(void *, long);
    512 int	ustore_uchar(void *, u_char);
    513 int	ustore_uchar_intrsafe(void *, u_char);
    514 int	ustore_ushort(void *, u_short);
    515 int	ustore_ushort_intrsafe(void *, u_short);
    516 int	ustore_uint(void *, u_int);
    517 int	ustore_uint_intrsafe(void *, u_int);
    518 int	ustore_ulong(void *, u_long);
    519 int	ustore_ulong_intrsafe(void *, u_long);
    520 int 	ustore_ptr(void *, void *);
    521 int	ustore_ptr_intrsafe(void *, void *);
    522 
    523 int	ustore_uint32_isync(void *, uint32_t);
    524 
    525 /* trap.c */
    526 void	netintr(void);
    527 int	kdbpeek(vaddr_t);
    528 
    529 /* mips_fpu.c */
    530 void	fpu_init(void);
    531 void	fpudiscard_lwp(struct lwp *);
    532 void	fpuload_lwp(struct lwp *);
    533 void	fpusave_lwp(struct lwp *);
    534 void	fpusave_cpu(struct cpu_info *);
    535 
    536 /* mips_machdep.c */
    537 struct mips_vmfreelist;
    538 struct phys_ram_seg;
    539 void	dumpsys(void);
    540 int	savectx(struct user *);
    541 void	mips_init_msgbuf(void);
    542 void	mips_init_lwp0_uarea(void);
    543 void	mips_page_physload(vaddr_t, vaddr_t,
    544 	    const struct phys_ram_seg *, size_t,
    545 	    const struct mips_vmfreelist *, size_t);
    546 void	cpu_identify(device_t);
    547 
    548 /* locore*.S */
    549 int	badaddr(void *, size_t);
    550 int	badaddr64(uint64_t, size_t);
    551 
    552 /* vm_machdep.c */
    553 void	cpu_uarea_remap(struct lwp *);
    554 
    555 #endif /* ! _LOCORE */
    556 #endif /* _KERNEL */
    557 #endif /* _CPU_H_ */
    558