cpu.h revision 1.90.16.34 1 /* $NetBSD: cpu.h,v 1.90.16.34 2011/02/08 06:01:08 cliff Exp $ */
2
3 /*-
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell and Rick Macklem.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94
35 */
36
37 #ifndef _CPU_H_
38 #define _CPU_H_
39
40 #include <mips/cpuregs.h>
41
42 /*
43 * Exported definitions unique to NetBSD/mips cpu support.
44 */
45
46 #ifdef _KERNEL
47
48 #ifndef _LOCORE
49 #if defined(_KERNEL_OPT)
50 #include "opt_cputype.h"
51 #include "opt_lockdebug.h"
52 #include "opt_multiprocessor.h"
53 #endif
54
55 #include <sys/cpu_data.h>
56 #include <sys/device.h>
57 #include <sys/evcnt.h>
58 #include <mips/reg.h>
59 #include <mips/cpuset.h>
60
61 struct cpu_info {
62 struct cpu_data ci_data; /* MI per-cpu data */
63 struct cpu_info *ci_next; /* Next CPU in list */
64 struct cpu_softc *ci_softc; /* chip-dependent hook */
65 device_t ci_dev; /* owning device */
66 cpuid_t ci_cpuid; /* Machine-level identifier */
67 u_long ci_cctr_freq; /* cycle counter frequency */
68 u_long ci_cpu_freq; /* CPU frequency */
69 u_long ci_cycles_per_hz; /* CPU freq / hz */
70 u_long ci_divisor_delay; /* for delay/DELAY */
71 u_long ci_divisor_recip; /* unused, for obsolete microtime(9) */
72 struct lwp *ci_curlwp; /* currently running lwp */
73 #ifndef NOFPU
74 struct lwp *ci_fpcurlwp; /* the current FPU owner */
75 #endif
76 volatile int ci_want_resched; /* user preemption pending */
77 int ci_mtx_count; /* negative count of held mutexes */
78 int ci_mtx_oldspl; /* saved SPL value */
79 int ci_idepth; /* hardware interrupt depth */
80 int ci_cpl; /* current [interrupt] priority level */
81 uint32_t ci_next_cp0_clk_intr; /* for hard clock intr scheduling */
82 struct evcnt ci_count_compare_evcnt; /* hard clock intr counter */
83 struct evcnt ci_count_compare_missed_evcnt; /* hard clock miss counter */
84 struct lwp *ci_softlwps[SOFTINT_COUNT];
85 #define ci_softints ci_data.cpu_softints
86
87 /*
88 * Per-cpu pmap information
89 */
90 int ci_tlb_slot; /* reserved tlb entry for cpu_info */
91 u_int ci_pmap_asid_cur; /* current ASID */
92 struct pmap_tlb_info *ci_tlb_info; /* tlb information for this cpu */
93 union segtab *ci_pmap_seg0tab;
94 #ifdef _LP64
95 union segtab *ci_pmap_segtab;
96 #else
97 vaddr_t ci_pmap_srcbase; /* starting VA of ephemeral src space */
98 vaddr_t ci_pmap_dstbase; /* starting VA of ephemeral dst space */
99 #endif
100
101
102 #ifdef MULTIPROCESSOR
103 volatile u_long ci_flags;
104 volatile uint64_t ci_request_ipis;
105 /* bitmask of IPIs requested */
106 /* use on chips where hw cannot pass tag */
107 uint64_t ci_active_ipis; /* bitmask of IPIs being serviced */
108 uint32_t ci_ksp_tlb_slot; /* tlb entry for kernel stack */
109 void *ci_fpsave_si; /* FP sync softint handler */
110 struct evcnt ci_evcnt_all_ipis; /* aggregated IPI counter */
111 struct evcnt ci_evcnt_per_ipi[NIPIS]; /* individual IPI counters*/
112 struct evcnt ci_evcnt_synci_activate_rqst;
113 struct evcnt ci_evcnt_synci_onproc_rqst;
114 struct evcnt ci_evcnt_synci_deferred_rqst;
115 struct evcnt ci_evcnt_synci_ipi_rqst;
116
117 #define CPUF_PRIMARY 0x01 /* CPU is primary CPU */
118 #define CPUF_PRESENT 0x02 /* CPU is present */
119 #define CPUF_RUNNING 0x04 /* CPU is running */
120 #define CPUF_PAUSED 0x08 /* CPU is paused */
121 #define CPUF_FPUSAVE 0x10 /* CPU is currently in fpusave_cpu() */
122 #define CPUF_USERPMAP 0x20 /* CPU has a user pmap activated */
123 #endif
124
125 };
126
127 #define CPU_INFO_ITERATOR int
128 #define CPU_INFO_FOREACH(cii, ci) \
129 (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next
130
131 #endif /* !_LOCORE */
132 #endif /* _KERNEL */
133
134 /*
135 * CTL_MACHDEP definitions.
136 */
137 #define CPU_CONSDEV 1 /* dev_t: console terminal device */
138 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */
139 #define CPU_ROOT_DEVICE 3 /* string: root device name */
140 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */
141
142 /*
143 * Platform can override, but note this breaks userland compatibility
144 * with other mips platforms.
145 */
146 #ifndef CPU_MAXID
147 #define CPU_MAXID 5 /* number of valid machdep ids */
148 #endif
149
150 #ifdef _KERNEL
151 #if defined(_LKM) || defined(_STANDALONE)
152 /* Assume all CPU architectures are valid for LKM's and standlone progs */
153 #define MIPS1 1
154 #define MIPS3 1
155 #define MIPS4 1
156 #define MIPS32 1
157 #define MIPS64 1
158 #endif
159
160 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0
161 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified
162 #endif
163
164 /* Shortcut for MIPS3 or above defined */
165 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)
166 #define MIPS3_PLUS 1
167 #define __HAVE_CPU_COUNTER
168 #else
169 #undef MIPS3_PLUS
170 #endif
171
172 /*
173 * Macros to find the CPU architecture we're on at run-time,
174 * or if possible, at compile-time.
175 */
176
177 #define CPU_ARCH_MIPSx 0 /* XXX unknown */
178 #define CPU_ARCH_MIPS1 (1 << 0)
179 #define CPU_ARCH_MIPS2 (1 << 1)
180 #define CPU_ARCH_MIPS3 (1 << 2)
181 #define CPU_ARCH_MIPS4 (1 << 3)
182 #define CPU_ARCH_MIPS5 (1 << 4)
183 #define CPU_ARCH_MIPS32 (1 << 5)
184 #define CPU_ARCH_MIPS64 (1 << 6)
185
186 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */
187 #define MIPS_CURLWP $24
188 #define MIPS_CURLWP_QUOTED "$24"
189 #define MIPS_CURLWP_LABEL _L_T8
190 #define MIPS_CURLWP_REG _R_T8
191 #define TF_MIPS_CURLWP(x) TF_REG_T8(x)
192
193 #ifndef _LOCORE
194
195 extern struct cpu_info cpu_info_store;
196 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED);
197
198 #define curlwp mips_curlwp
199 #define curcpu() (curlwp->l_cpu)
200 #define curpcb (&curlwp->l_addr->u_pcb)
201 #ifdef MULTIPROCESSOR
202 #define cpu_number() (curcpu()->ci_index)
203 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY)
204 #else
205 #define cpu_number() (0L)
206 #endif
207
208 /* XXX simonb
209 * Should the following be in a cpu_info type structure?
210 * And how many of these are per-cpu vs. per-system? (Ie,
211 * we can assume that all cpus have the same mmu-type, but
212 * maybe not that all cpus run at the same clock speed.
213 * Some SGI's apparently support R12k and R14k in the same
214 * box.)
215 */
216 struct mips_options {
217 const struct pridtab *mips_cpu;
218
219 u_int mips_cpu_arch;
220 u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */
221 u_int mips_cpu_flags;
222 u_int mips_num_tlb_entries;
223 mips_prid_t mips_cpu_id;
224 mips_prid_t mips_fpu_id;
225 bool mips_has_r4k_mmu;
226 bool mips_has_llsc;
227 u_int mips3_pg_shift;
228 u_int mips3_pg_cached;
229 #ifdef MIPS3_PLUS
230 #ifdef _LP64
231 uint64_t mips3_xkphys_cached;
232 #endif
233 uint64_t mips3_tlb_vpn_mask;
234 uint64_t mips3_tlb_pfn_mask;
235 uint32_t mips3_tlb_pg_mask;
236 #endif
237 };
238 extern struct mips_options mips_options;
239
240 #define CPU_MIPS_R4K_MMU 0x0001
241 #define CPU_MIPS_NO_LLSC 0x0002
242 #define CPU_MIPS_CAUSE_IV 0x0004
243 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */
244 #define CPU_MIPS_CACHED_CCA_MASK 0x0070
245 #define CPU_MIPS_CACHED_CCA_SHIFT 4
246 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */
247 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */
248 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */
249 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */
250 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */
251 #define CPU_MIPS_NO_LLADDR 0x1000
252 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */
253 #define MIPS_NOT_SUPP 0x8000
254
255 #endif /* !_LOCORE */
256
257 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE)
258
259 #if defined(MIPS1)
260
261 # define CPUISMIPS3 0
262 # define CPUIS64BITS 0
263 # define CPUISMIPS32 0
264 # define CPUISMIPS64 0
265 # define CPUISMIPSNN 0
266 # define MIPS_HAS_R4K_MMU 0
267 # define MIPS_HAS_CLOCK 0
268 # define MIPS_HAS_LLSC 0
269 # define MIPS_HAS_LLADDR 0
270
271 #elif defined(MIPS3) || defined(MIPS4)
272
273 # define CPUISMIPS3 1
274 # define CPUIS64BITS 1
275 # define CPUISMIPS32 0
276 # define CPUISMIPS64 0
277 # define CPUISMIPSNN 0
278 # define MIPS_HAS_R4K_MMU 1
279 # define MIPS_HAS_CLOCK 1
280 # if defined(_LOCORE)
281 # if !defined(MIPS3_5900) && !defined(MIPS3_4100)
282 # define MIPS_HAS_LLSC 1
283 # else
284 # define MIPS_HAS_LLSC 0
285 # endif
286 # else /* _LOCORE */
287 # define MIPS_HAS_LLSC (mips_options.mips_has_llsc)
288 # endif /* _LOCORE */
289 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
290
291 #elif defined(MIPS32)
292
293 # define CPUISMIPS3 1
294 # define CPUIS64BITS 0
295 # define CPUISMIPS32 1
296 # define CPUISMIPS64 0
297 # define CPUISMIPSNN 1
298 # define MIPS_HAS_R4K_MMU 1
299 # define MIPS_HAS_CLOCK 1
300 # define MIPS_HAS_LLSC 1
301 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
302
303 #elif defined(MIPS64)
304
305 # define CPUISMIPS3 1
306 # define CPUIS64BITS 1
307 # define CPUISMIPS32 0
308 # define CPUISMIPS64 1
309 # define CPUISMIPSNN 1
310 # define MIPS_HAS_R4K_MMU 1
311 # define MIPS_HAS_CLOCK 1
312 # define MIPS_HAS_LLSC 1
313 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
314
315 #endif
316
317 #else /* run-time test */
318
319 #ifndef _LOCORE
320
321 #define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu)
322 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc)
323 #define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
324
325 /* This test is ... rather bogus */
326 #define CPUISMIPS3 ((mips_options.mips_cpu_arch & \
327 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0)
328
329 /* And these aren't much better while the previous test exists as is... */
330 #define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0)
331 #define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0)
332 #define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0)
333 #define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0)
334 #define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0)
335 #define CPUIS64BITS ((mips_options.mips_cpu_arch & \
336 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0)
337
338 #define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3)
339
340 #else /* !_LOCORE */
341
342 #define MIPS_HAS_LLSC 0
343
344 #endif /* !_LOCORE */
345
346 #endif /* run-time test */
347
348 #ifndef _LOCORE
349
350 /*
351 * definitions of cpu-dependent requirements
352 * referenced in generic code
353 */
354 #define cpu_swapout(p) panic("cpu_swapout: can't get here");
355
356 /*
357 * Send an inter-processor interupt to each other CPU (excludes curcpu())
358 */
359 void cpu_broadcast_ipi(int);
360
361 /*
362 * Send an inter-processor interupt to CPUs in cpuset (excludes curcpu())
363 */
364 void cpu_multicast_ipi(mips_cpuset_t, int);
365
366 /*
367 * Send an inter-processor interupt to another CPU.
368 */
369 int cpu_send_ipi(struct cpu_info *, int);
370
371 /*
372 * cpu_intr(ppl, pc, status); (most state needed by clockframe)
373 */
374 void cpu_intr(int, vaddr_t, uint32_t);
375
376 /*
377 * Arguments to hardclock and gatherstats encapsulate the previous
378 * machine state in an opaque clockframe.
379 */
380 struct clockframe {
381 vaddr_t pc; /* program counter at time of interrupt */
382 uint32_t sr; /* status register at time of interrupt */
383 bool intr; /* interrupted a interrupt */
384 };
385
386 /*
387 * A port must provde CLKF_USERMODE() for use in machine-independent code.
388 * These differ on r4000 and r3000 systems; provide them in the
389 * port-dependent file that includes this one, using the macros below.
390 */
391
392 /* mips1 versions */
393 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV)
394
395 /* mips3 versions */
396 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER)
397
398 #define CLKF_PC(framep) ((framep)->pc)
399 #define CLKF_INTR(framep) ((framep)->intr)
400
401 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */
402 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep)
403 #endif
404
405 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */
406 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep)
407 #endif
408
409 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */
410 #define CLKF_USERMODE(framep) \
411 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep))
412 #endif
413
414 /*
415 * Misc prototypes and variable declarations.
416 */
417 struct lwp;
418 struct user;
419
420 /*
421 * Preempt the current process if in interrupt from user mode,
422 * or after the current trap/syscall if in system mode.
423 */
424 void cpu_need_resched(struct cpu_info *, int);
425 /*
426 * Notify the current lwp (l) that it has a signal pending,
427 * process as soon as possible.
428 */
429 void cpu_signotify(struct lwp *);
430
431 /*
432 * Give a profiling tick to the current process when the user profiling
433 * buffer pages are invalid. On the MIPS, request an ast to send us
434 * through trap, marking the proc as needing a profiling tick.
435 */
436 void cpu_need_proftick(struct lwp *);
437 void cpu_set_curpri(int);
438
439 extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */
440
441 struct cpu_info *
442 cpu_info_alloc(struct pmap_tlb_info *, cpuid_t, cpuid_t, cpuid_t,
443 cpuid_t);
444 void cpu_attach_common(device_t, struct cpu_info *);
445 void cpu_startup_common(void);
446 #ifdef _LP64
447 void cpu_vmspace_exec(struct lwp *, vaddr_t, vaddr_t);
448 #endif
449
450 #ifdef MULTIPROCESSOR
451 void cpu_hatch(struct cpu_info *ci);
452 void cpu_trampoline(void);
453 void cpu_boot_secondary_processors(void);
454 void cpu_halt(void);
455 void cpu_halt_others(void);
456 void cpu_pause(struct reg *);
457 void cpu_pause_others(void);
458 void cpu_resume(int);
459 void cpu_resume_others(void);
460 int cpu_is_paused(int);
461 void cpu_debug_dump(void);
462
463 extern volatile mips_cpuset_t cpus_running;
464 extern volatile mips_cpuset_t cpus_hatched;
465 extern volatile mips_cpuset_t cpus_paused;
466 extern volatile mips_cpuset_t cpus_resumed;
467 extern volatile mips_cpuset_t cpus_halted;
468 #endif
469
470 /* copy.S */
471 int8_t ufetch_int8(void *);
472 int16_t ufetch_int16(void *);
473 int32_t ufetch_int32(void *);
474 uint8_t ufetch_uint8(void *);
475 uint16_t ufetch_uint16(void *);
476 uint32_t ufetch_uint32(void *);
477 int8_t ufetch_int8_intrsafe(void *);
478 int16_t ufetch_int16_intrsafe(void *);
479 int32_t ufetch_int32_intrsafe(void *);
480 uint8_t ufetch_uint8_intrsafe(void *);
481 uint16_t ufetch_uint16_intrsafe(void *);
482 uint32_t ufetch_uint32_intrsafe(void *);
483 #ifdef _LP64
484 int64_t ufetch_int64(void *);
485 uint64_t ufetch_uint64(void *);
486 int64_t ufetch_int64_intrsafe(void *);
487 uint64_t ufetch_uint64_intrsafe(void *);
488 #endif
489 char ufetch_char(void *);
490 short ufetch_short(void *);
491 int ufetch_int(void *);
492 long ufetch_long(void *);
493 char ufetch_char_intrsafe(void *);
494 short ufetch_short_intrsafe(void *);
495 int ufetch_int_intrsafe(void *);
496 long ufetch_long_intrsafe(void *);
497
498 u_char ufetch_uchar(void *);
499 u_short ufetch_ushort(void *);
500 u_int ufetch_uint(void *);
501 u_long ufetch_ulong(void *);
502 u_char ufetch_uchar_intrsafe(void *);
503 u_short ufetch_ushort_intrsafe(void *);
504 u_int ufetch_uint_intrsafe(void *);
505 u_long ufetch_ulong_intrsafe(void *);
506 void *ufetch_ptr(void *);
507
508 int ustore_int8(void *, int8_t);
509 int ustore_int16(void *, int16_t);
510 int ustore_int32(void *, int32_t);
511 int ustore_uint8(void *, uint8_t);
512 int ustore_uint16(void *, uint16_t);
513 int ustore_uint32(void *, uint32_t);
514 int ustore_int8_intrsafe(void *, int8_t);
515 int ustore_int16_intrsafe(void *, int16_t);
516 int ustore_int32_intrsafe(void *, int32_t);
517 int ustore_uint8_intrsafe(void *, uint8_t);
518 int ustore_uint16_intrsafe(void *, uint16_t);
519 int ustore_uint32_intrsafe(void *, uint32_t);
520 #ifdef _LP64
521 int ustore_int64(void *, int64_t);
522 int ustore_uint64(void *, uint64_t);
523 int ustore_int64_intrsafe(void *, int64_t);
524 int ustore_uint64_intrsafe(void *, uint64_t);
525 #endif
526 int ustore_char(void *, char);
527 int ustore_char_intrsafe(void *, char);
528 int ustore_short(void *, short);
529 int ustore_short_intrsafe(void *, short);
530 int ustore_int(void *, int);
531 int ustore_int_intrsafe(void *, int);
532 int ustore_long(void *, long);
533 int ustore_long_intrsafe(void *, long);
534 int ustore_uchar(void *, u_char);
535 int ustore_uchar_intrsafe(void *, u_char);
536 int ustore_ushort(void *, u_short);
537 int ustore_ushort_intrsafe(void *, u_short);
538 int ustore_uint(void *, u_int);
539 int ustore_uint_intrsafe(void *, u_int);
540 int ustore_ulong(void *, u_long);
541 int ustore_ulong_intrsafe(void *, u_long);
542 int ustore_ptr(void *, void *);
543 int ustore_ptr_intrsafe(void *, void *);
544
545 int ustore_uint32_isync(void *, uint32_t);
546
547 /* trap.c */
548 void netintr(void);
549 int kdbpeek(vaddr_t);
550
551 /* mips_fpu.c */
552 void fpu_init(void);
553 void fpudiscard_lwp(struct lwp *);
554 void fpuload_lwp(struct lwp *);
555 void fpusave_lwp(struct lwp *);
556 void fpusave_cpu(struct cpu_info *);
557
558 /* mips_machdep.c */
559 struct mips_vmfreelist;
560 struct phys_ram_seg;
561 void dumpsys(void);
562 int savectx(struct user *);
563 void mips_init_msgbuf(void);
564 void mips_init_lwp0_uarea(void);
565 void mips_page_physload(vaddr_t, vaddr_t,
566 const struct phys_ram_seg *, size_t,
567 const struct mips_vmfreelist *, size_t);
568 void cpu_identify(device_t);
569
570 /* locore*.S */
571 int badaddr(void *, size_t);
572 int badaddr64(uint64_t, size_t);
573
574 /* vm_machdep.c */
575 void cpu_uarea_remap(struct lwp *);
576
577 #endif /* ! _LOCORE */
578 #endif /* _KERNEL */
579 #endif /* _CPU_H_ */
580