cpu.h revision 1.90.16.36
1 /* $NetBSD: cpu.h,v 1.90.16.36 2011/04/29 08:26:20 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 48 #if defined(_KERNEL_OPT) 49 #include "opt_cputype.h" 50 #include "opt_lockdebug.h" 51 #include "opt_multiprocessor.h" 52 #endif 53 54 #ifndef _LOCORE 55 #include <sys/cpu_data.h> 56 #include <sys/device.h> 57 #include <sys/evcnt.h> 58 59 typedef struct cpu_watchpoint { 60 register_t cw_addr; 61 register_t cw_mask; 62 uint32_t cw_asid; 63 uint32_t cw_mode; 64 } cpu_watchpoint_t; 65 /* (abstract) mode bits */ 66 #define CPUWATCH_WRITE __BIT(0) 67 #define CPUWATCH_READ __BIT(1) 68 #define CPUWATCH_EXEC __BIT(2) 69 #define CPUWATCH_MASK __BIT(3) 70 #define CPUWATCH_ASID __BIT(4) 71 #define CPUWATCH_RWX (CPUWATCH_EXEC|CPUWATCH_READ|CPUWATCH_WRITE) 72 73 #define CPUWATCH_MAX 8 /* max possible number of watchpoints */ 74 75 u_int cpuwatch_discover(void); 76 void cpuwatch_free(cpu_watchpoint_t *); 77 cpu_watchpoint_t *cpuwatch_alloc(void); 78 void cpuwatch_set_all(void); 79 void cpuwatch_clr_all(void); 80 void cpuwatch_set(cpu_watchpoint_t *); 81 void cpuwatch_clr(cpu_watchpoint_t *); 82 83 struct cpu_info { 84 struct cpu_data ci_data; /* MI per-cpu data */ 85 struct cpu_info *ci_next; /* Next CPU in list */ 86 struct cpu_softc *ci_softc; /* chip-dependent hook */ 87 device_t ci_dev; /* owning device */ 88 cpuid_t ci_cpuid; /* Machine-level identifier */ 89 u_long ci_cctr_freq; /* cycle counter frequency */ 90 u_long ci_cpu_freq; /* CPU frequency */ 91 u_long ci_cycles_per_hz; /* CPU freq / hz */ 92 u_long ci_divisor_delay; /* for delay/DELAY */ 93 u_long ci_divisor_recip; /* unused, for obsolete microtime(9) */ 94 struct lwp *ci_curlwp; /* currently running lwp */ 95 #ifndef NOFPU 96 struct lwp *ci_fpcurlwp; /* the current FPU owner */ 97 #endif 98 volatile int ci_want_resched; /* user preemption pending */ 99 int ci_mtx_count; /* negative count of held mutexes */ 100 int ci_mtx_oldspl; /* saved SPL value */ 101 int ci_idepth; /* hardware interrupt depth */ 102 int ci_cpl; /* current [interrupt] priority level */ 103 uint32_t ci_next_cp0_clk_intr; /* for hard clock intr scheduling */ 104 struct evcnt ci_ev_count_compare; /* hard clock intr counter */ 105 struct evcnt ci_ev_count_compare_missed; /* hard clock miss counter */ 106 struct lwp *ci_softlwps[SOFTINT_COUNT]; 107 volatile u_int ci_softints; 108 struct evcnt ci_ev_fpu_loads; /* fpu load counter */ 109 struct evcnt ci_ev_fpu_saves; /* fpu save counter */ 110 struct evcnt ci_ev_tlbmisses; 111 112 /* 113 * Per-cpu pmap information 114 */ 115 int ci_tlb_slot; /* reserved tlb entry for cpu_info */ 116 u_int ci_pmap_asid_cur; /* current ASID */ 117 struct pmap_tlb_info *ci_tlb_info; /* tlb information for this cpu */ 118 union segtab *ci_pmap_seg0tab; 119 #ifdef _LP64 120 union segtab *ci_pmap_segtab; 121 #else 122 vaddr_t ci_pmap_srcbase; /* starting VA of ephemeral src space */ 123 vaddr_t ci_pmap_dstbase; /* starting VA of ephemeral dst space */ 124 #endif 125 126 u_int ci_cpuwatch_count; /* number of watchpoints on this CPU */ 127 cpu_watchpoint_t ci_cpuwatch_tab[CPUWATCH_MAX]; 128 129 #ifdef MULTIPROCESSOR 130 volatile u_long ci_flags; 131 volatile uint64_t ci_request_ipis; 132 /* bitmask of IPIs requested */ 133 /* use on chips where hw cannot pass tag */ 134 uint64_t ci_active_ipis; /* bitmask of IPIs being serviced */ 135 uint32_t ci_ksp_tlb_slot; /* tlb entry for kernel stack */ 136 void *ci_fpsave_si; /* FP sync softint handler */ 137 struct evcnt ci_evcnt_all_ipis; /* aggregated IPI counter */ 138 struct evcnt ci_evcnt_per_ipi[NIPIS]; /* individual IPI counters*/ 139 struct evcnt ci_evcnt_synci_activate_rqst; 140 struct evcnt ci_evcnt_synci_onproc_rqst; 141 struct evcnt ci_evcnt_synci_deferred_rqst; 142 struct evcnt ci_evcnt_synci_ipi_rqst; 143 144 #define CPUF_PRIMARY 0x01 /* CPU is primary CPU */ 145 #define CPUF_PRESENT 0x02 /* CPU is present */ 146 #define CPUF_RUNNING 0x04 /* CPU is running */ 147 #define CPUF_PAUSED 0x08 /* CPU is paused */ 148 #define CPUF_FPUSAVE 0x10 /* CPU is currently in fpusave_cpu() */ 149 #define CPUF_USERPMAP 0x20 /* CPU has a user pmap activated */ 150 #endif 151 152 }; 153 154 #define CPU_INFO_ITERATOR int 155 #define CPU_INFO_FOREACH(cii, ci) \ 156 (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next 157 158 #endif /* !_LOCORE */ 159 #endif /* _KERNEL */ 160 161 /* 162 * CTL_MACHDEP definitions. 163 */ 164 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 165 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 166 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 167 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 168 169 /* 170 * Platform can override, but note this breaks userland compatibility 171 * with other mips platforms. 172 */ 173 #ifndef CPU_MAXID 174 #define CPU_MAXID 5 /* number of valid machdep ids */ 175 #endif 176 177 #ifdef _KERNEL 178 #if defined(_MODULAR) || defined(_LKM) || defined(_STANDALONE) 179 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 180 #define MIPS1 1 181 #define MIPS3 1 182 #define MIPS4 1 183 #define MIPS32 1 184 #define MIPS32R2 1 185 #define MIPS64 1 186 #define MIPS64R2 1 187 #endif 188 189 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0 190 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32, MIPS32R2, MIPS64, or MIPS64RR2 must be specified 191 #endif 192 193 /* Shortcut for MIPS3 or above defined */ 194 #if defined(MIPS3) || defined(MIPS4) \ 195 || defined(MIPS32) || defined(MIPS32R2) \ 196 || defined(MIPS64) || defined(MIPS64R2) 197 198 #define MIPS3_PLUS 1 199 #define __HAVE_CPU_COUNTER 200 #else 201 #undef MIPS3_PLUS 202 #endif 203 204 /* 205 * Macros to find the CPU architecture we're on at run-time, 206 * or if possible, at compile-time. 207 */ 208 209 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 210 #define CPU_ARCH_MIPS1 (1 << 0) 211 #define CPU_ARCH_MIPS2 (1 << 1) 212 #define CPU_ARCH_MIPS3 (1 << 2) 213 #define CPU_ARCH_MIPS4 (1 << 3) 214 #define CPU_ARCH_MIPS5 (1 << 4) 215 #define CPU_ARCH_MIPS32 (1 << 5) 216 #define CPU_ARCH_MIPS64 (1 << 6) 217 #define CPU_ARCH_MIPS32R2 (1 << 7) 218 #define CPU_ARCH_MIPS64R2 (1 << 8) 219 220 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 221 #define MIPS_CURLWP $24 222 #define MIPS_CURLWP_QUOTED "$24" 223 #define MIPS_CURLWP_LABEL _L_T8 224 #define MIPS_CURLWP_REG _R_T8 225 #define TF_MIPS_CURLWP(x) TF_REG_T8(x) 226 227 #ifndef _LOCORE 228 229 extern struct cpu_info cpu_info_store; 230 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 231 232 #define curlwp mips_curlwp 233 #define curcpu() (curlwp->l_cpu) 234 #define curpcb ((struct pcb *)lwp_getpcb(curlwp)) 235 #ifdef MULTIPROCESSOR 236 #define cpu_number() (curcpu()->ci_index) 237 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 238 #else 239 #define cpu_number() (0) 240 #define CPU_IS_PRIMARY(ci) (true) 241 #endif 242 243 /* XXX simonb 244 * Should the following be in a cpu_info type structure? 245 * And how many of these are per-cpu vs. per-system? (Ie, 246 * we can assume that all cpus have the same mmu-type, but 247 * maybe not that all cpus run at the same clock speed. 248 * Some SGI's apparently support R12k and R14k in the same 249 * box.) 250 */ 251 struct mips_options { 252 const struct pridtab *mips_cpu; 253 254 u_int mips_cpu_arch; 255 u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */ 256 u_int mips_cpu_flags; 257 u_int mips_num_tlb_entries; 258 mips_prid_t mips_cpu_id; 259 mips_prid_t mips_fpu_id; 260 bool mips_has_r4k_mmu; 261 bool mips_has_llsc; 262 u_int mips3_pg_shift; 263 u_int mips3_pg_cached; 264 #ifdef MIPS3_PLUS 265 #ifdef _LP64 266 uint64_t mips3_xkphys_cached; 267 #endif 268 uint64_t mips3_tlb_vpn_mask; 269 uint64_t mips3_tlb_pfn_mask; 270 uint32_t mips3_tlb_pg_mask; 271 #endif 272 }; 273 extern struct mips_options mips_options; 274 275 #define CPU_MIPS_R4K_MMU 0x0001 276 #define CPU_MIPS_NO_LLSC 0x0002 277 #define CPU_MIPS_CAUSE_IV 0x0004 278 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 279 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 280 #define CPU_MIPS_CACHED_CCA_SHIFT 4 281 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 282 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 283 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 284 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 285 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 286 #define CPU_MIPS_NO_LLADDR 0x1000 287 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 288 #define MIPS_NOT_SUPP 0x8000 289 290 #endif /* !_LOCORE */ 291 292 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 1) || defined(_LOCORE) 293 294 #if defined(MIPS1) 295 296 # define CPUISMIPS3 0 297 # define CPUIS64BITS 0 298 # define CPUISMIPS32 0 299 # define CPUISMIPS32R2 0 300 # define CPUISMIPS64 0 301 # define CPUISMIPS64R2 0 302 # define CPUISMIPSNN 0 303 # define MIPS_HAS_R4K_MMU 0 304 # define MIPS_HAS_CLOCK 0 305 # define MIPS_HAS_LLSC 0 306 # define MIPS_HAS_LLADDR 0 307 308 #elif defined(MIPS3) || defined(MIPS4) 309 310 # define CPUISMIPS3 1 311 # define CPUIS64BITS 1 312 # define CPUISMIPS32 0 313 # define CPUISMIPS32R2 0 314 # define CPUISMIPS64 0 315 # define CPUISMIPS64R2 0 316 # define CPUISMIPSNN 0 317 # define MIPS_HAS_R4K_MMU 1 318 # define MIPS_HAS_CLOCK 1 319 # if defined(_LOCORE) 320 # if !defined(MIPS3_4100) 321 # define MIPS_HAS_LLSC 1 322 # else 323 # define MIPS_HAS_LLSC 0 324 # endif 325 # else /* _LOCORE */ 326 # define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 327 # endif /* _LOCORE */ 328 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 329 330 #elif defined(MIPS32) 331 332 # define CPUISMIPS3 1 333 # define CPUIS64BITS 0 334 # define CPUISMIPS32 1 335 # define CPUISMIPS32R2 0 336 # define CPUISMIPS64 0 337 # define CPUISMIPS64R2 0 338 # define CPUISMIPSNN 1 339 # define MIPS_HAS_R4K_MMU 1 340 # define MIPS_HAS_CLOCK 1 341 # define MIPS_HAS_LLSC 1 342 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 343 344 #elif defined(MIPS32R2) 345 346 # define CPUISMIPS3 1 347 # define CPUIS64BITS 0 348 # define CPUISMIPS32 0 349 # define CPUISMIPS32R2 1 350 # define CPUISMIPS64 0 351 # define CPUISMIPS64R2 0 352 # define CPUISMIPSNN 1 353 # define MIPS_HAS_R4K_MMU 1 354 # define MIPS_HAS_CLOCK 1 355 # define MIPS_HAS_LLSC 1 356 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 357 358 #elif defined(MIPS64) 359 360 # define CPUISMIPS3 1 361 # define CPUIS64BITS 1 362 # define CPUISMIPS32 0 363 # define CPUISMIPS32R2 0 364 # define CPUISMIPS64 1 365 # define CPUISMIPS64R2 0 366 # define CPUISMIPSNN 1 367 # define MIPS_HAS_R4K_MMU 1 368 # define MIPS_HAS_CLOCK 1 369 # define MIPS_HAS_LLSC 1 370 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 371 372 #elif defined(MIPS64R2) 373 374 # define CPUISMIPS3 1 375 # define CPUIS64BITS 1 376 # define CPUISMIPS32 0 377 # define CPUISMIPS32R2 0 378 # define CPUISMIPS64 0 379 # define CPUISMIPS64R2 1 380 # define CPUISMIPSNN 1 381 # define MIPS_HAS_R4K_MMU 1 382 # define MIPS_HAS_CLOCK 1 383 # define MIPS_HAS_LLSC 1 384 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 385 386 #endif 387 388 #else /* run-time test */ 389 390 #ifndef _LOCORE 391 392 #define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu) 393 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 394 #define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 395 396 /* This test is ... rather bogus */ 397 #define CPUISMIPS3 ((mips_options.mips_cpu_arch & \ 398 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 399 400 /* And these aren't much better while the previous test exists as is... */ 401 #define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0) 402 #define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0) 403 #define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0) 404 #define CPUISMIPS32R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32R2) != 0) 405 #define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0) 406 #define CPUISMIPS64R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64R2) != 0) 407 #define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS32R2 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 408 #define CPUIS64BITS ((mips_options.mips_cpu_arch & \ 409 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 410 411 #define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) 412 413 #else /* !_LOCORE */ 414 415 #define MIPS_HAS_LLSC 0 416 417 #endif /* !_LOCORE */ 418 419 #endif /* run-time test */ 420 421 #ifndef _LOCORE 422 423 /* 424 * definitions of cpu-dependent requirements 425 * referenced in generic code 426 */ 427 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 428 429 /* 430 * Send an inter-processor interupt to each other CPU (excludes curcpu()) 431 */ 432 void cpu_broadcast_ipi(int); 433 434 /* 435 * Send an inter-processor interupt to CPUs in cpuset (excludes curcpu()) 436 */ 437 void cpu_multicast_ipi(__cpuset_t, int); 438 439 /* 440 * Send an inter-processor interupt to another CPU. 441 */ 442 int cpu_send_ipi(struct cpu_info *, int); 443 444 /* 445 * cpu_intr(ppl, pc, status); (most state needed by clockframe) 446 */ 447 void cpu_intr(int, vaddr_t, uint32_t); 448 449 /* 450 * Arguments to hardclock and gatherstats encapsulate the previous 451 * machine state in an opaque clockframe. 452 */ 453 struct clockframe { 454 vaddr_t pc; /* program counter at time of interrupt */ 455 uint32_t sr; /* status register at time of interrupt */ 456 bool intr; /* interrupted a interrupt */ 457 }; 458 459 /* 460 * A port must provde CLKF_USERMODE() for use in machine-independent code. 461 * These differ on r4000 and r3000 systems; provide them in the 462 * port-dependent file that includes this one, using the macros below. 463 */ 464 465 /* mips1 versions */ 466 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 467 468 /* mips3 versions */ 469 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 470 471 #define CLKF_PC(framep) ((framep)->pc) 472 #define CLKF_INTR(framep) ((framep)->intr) 473 474 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 475 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 476 #endif 477 478 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 479 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 480 #endif 481 482 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 483 #define CLKF_USERMODE(framep) \ 484 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 485 #endif 486 487 /* 488 * Misc prototypes and variable declarations. 489 */ 490 #define LWP_PC(l) cpu_lwp_pc(l) 491 492 struct proc; 493 struct lwp; 494 struct pcb; 495 struct reg; 496 497 /* 498 * Preempt the current process if in interrupt from user mode, 499 * or after the current trap/syscall if in system mode. 500 */ 501 void cpu_need_resched(struct cpu_info *, int); 502 /* 503 * Notify the current lwp (l) that it has a signal pending, 504 * process as soon as possible. 505 */ 506 void cpu_signotify(struct lwp *); 507 508 /* 509 * Give a profiling tick to the current process when the user profiling 510 * buffer pages are invalid. On the MIPS, request an ast to send us 511 * through trap, marking the proc as needing a profiling tick. 512 */ 513 void cpu_need_proftick(struct lwp *); 514 void cpu_set_curpri(int); 515 516 extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */ 517 518 struct cpu_info * 519 cpu_info_alloc(struct pmap_tlb_info *, cpuid_t, cpuid_t, cpuid_t, 520 cpuid_t); 521 void cpu_attach_common(device_t, struct cpu_info *); 522 void cpu_startup_common(void); 523 #ifdef _LP64 524 void cpu_vmspace_exec(struct lwp *, vaddr_t, vaddr_t); 525 #endif 526 527 #ifdef MULTIPROCESSOR 528 void cpu_hatch(struct cpu_info *ci); 529 void cpu_trampoline(void); 530 void cpu_boot_secondary_processors(void); 531 void cpu_halt(void); 532 void cpu_halt_others(void); 533 void cpu_pause(struct reg *); 534 void cpu_pause_others(void); 535 void cpu_resume(int); 536 void cpu_resume_others(void); 537 int cpu_is_paused(int); 538 void cpu_debug_dump(void); 539 540 extern volatile __cpuset_t cpus_running; 541 extern volatile __cpuset_t cpus_hatched; 542 extern volatile __cpuset_t cpus_paused; 543 extern volatile __cpuset_t cpus_resumed; 544 extern volatile __cpuset_t cpus_halted; 545 #endif 546 547 /* copy.S */ 548 int8_t ufetch_int8(void *); 549 int16_t ufetch_int16(void *); 550 int32_t ufetch_int32(void *); 551 uint8_t ufetch_uint8(void *); 552 uint16_t ufetch_uint16(void *); 553 uint32_t ufetch_uint32(void *); 554 int8_t ufetch_int8_intrsafe(void *); 555 int16_t ufetch_int16_intrsafe(void *); 556 int32_t ufetch_int32_intrsafe(void *); 557 uint8_t ufetch_uint8_intrsafe(void *); 558 uint16_t ufetch_uint16_intrsafe(void *); 559 uint32_t ufetch_uint32_intrsafe(void *); 560 #ifdef _LP64 561 int64_t ufetch_int64(void *); 562 uint64_t ufetch_uint64(void *); 563 int64_t ufetch_int64_intrsafe(void *); 564 uint64_t ufetch_uint64_intrsafe(void *); 565 #endif 566 char ufetch_char(void *); 567 short ufetch_short(void *); 568 int ufetch_int(void *); 569 long ufetch_long(void *); 570 char ufetch_char_intrsafe(void *); 571 short ufetch_short_intrsafe(void *); 572 int ufetch_int_intrsafe(void *); 573 long ufetch_long_intrsafe(void *); 574 575 u_char ufetch_uchar(void *); 576 u_short ufetch_ushort(void *); 577 u_int ufetch_uint(void *); 578 u_long ufetch_ulong(void *); 579 u_char ufetch_uchar_intrsafe(void *); 580 u_short ufetch_ushort_intrsafe(void *); 581 u_int ufetch_uint_intrsafe(void *); 582 u_long ufetch_ulong_intrsafe(void *); 583 void *ufetch_ptr(void *); 584 585 int ustore_int8(void *, int8_t); 586 int ustore_int16(void *, int16_t); 587 int ustore_int32(void *, int32_t); 588 int ustore_uint8(void *, uint8_t); 589 int ustore_uint16(void *, uint16_t); 590 int ustore_uint32(void *, uint32_t); 591 int ustore_int8_intrsafe(void *, int8_t); 592 int ustore_int16_intrsafe(void *, int16_t); 593 int ustore_int32_intrsafe(void *, int32_t); 594 int ustore_uint8_intrsafe(void *, uint8_t); 595 int ustore_uint16_intrsafe(void *, uint16_t); 596 int ustore_uint32_intrsafe(void *, uint32_t); 597 #ifdef _LP64 598 int ustore_int64(void *, int64_t); 599 int ustore_uint64(void *, uint64_t); 600 int ustore_int64_intrsafe(void *, int64_t); 601 int ustore_uint64_intrsafe(void *, uint64_t); 602 #endif 603 int ustore_char(void *, char); 604 int ustore_char_intrsafe(void *, char); 605 int ustore_short(void *, short); 606 int ustore_short_intrsafe(void *, short); 607 int ustore_int(void *, int); 608 int ustore_int_intrsafe(void *, int); 609 int ustore_long(void *, long); 610 int ustore_long_intrsafe(void *, long); 611 int ustore_uchar(void *, u_char); 612 int ustore_uchar_intrsafe(void *, u_char); 613 int ustore_ushort(void *, u_short); 614 int ustore_ushort_intrsafe(void *, u_short); 615 int ustore_uint(void *, u_int); 616 int ustore_uint_intrsafe(void *, u_int); 617 int ustore_ulong(void *, u_long); 618 int ustore_ulong_intrsafe(void *, u_long); 619 int ustore_ptr(void *, void *); 620 int ustore_ptr_intrsafe(void *, void *); 621 622 int ustore_uint32_isync(void *, uint32_t); 623 624 /* trap.c */ 625 void netintr(void); 626 int kdbpeek(vaddr_t); 627 628 /* mips_fpu.c */ 629 void fpu_init(void); 630 void fpu_discard(void); 631 void fpu_load(void); 632 void fpu_save(void); 633 void fpu_save_lwp(struct lwp *); 634 void fpusave_cpu(struct cpu_info *); 635 636 /* mips_machdep.c */ 637 void dumpsys(void); 638 int savectx(struct pcb *); 639 void cpu_identify(device_t); 640 641 /* locore*.S */ 642 int badaddr(void *, size_t); 643 int badaddr64(uint64_t, size_t); 644 645 /* vm_machdep.c */ 646 void cpu_proc_fork(struct proc *, struct proc *); 647 vaddr_t cpu_lwp_pc(struct lwp *); 648 void cpu_uarea_remap(struct lwp *); 649 650 #endif /* ! _LOCORE */ 651 #endif /* _KERNEL */ 652 #endif /* _CPU_H_ */ 653
Indexes created Mon Oct 13 01:09:56 GMT 2025