cpu.h revision 1.90.16.37
1 /* cpu.h,v 1.90.16.36 2011/04/29 08:26:20 matt Exp */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 48 #if defined(_KERNEL_OPT) 49 #include "opt_cputype.h" 50 #include "opt_lockdebug.h" 51 #include "opt_multiprocessor.h" 52 #endif 53 54 #ifndef _LOCORE 55 #include <sys/cpu_data.h> 56 #include <sys/device.h> 57 #include <sys/evcnt.h> 58 59 typedef struct cpu_watchpoint { 60 register_t cw_addr; 61 register_t cw_mask; 62 uint32_t cw_asid; 63 uint32_t cw_mode; 64 } cpu_watchpoint_t; 65 /* (abstract) mode bits */ 66 #define CPUWATCH_WRITE __BIT(0) 67 #define CPUWATCH_READ __BIT(1) 68 #define CPUWATCH_EXEC __BIT(2) 69 #define CPUWATCH_MASK __BIT(3) 70 #define CPUWATCH_ASID __BIT(4) 71 #define CPUWATCH_RWX (CPUWATCH_EXEC|CPUWATCH_READ|CPUWATCH_WRITE) 72 73 #define CPUWATCH_MAX 8 /* max possible number of watchpoints */ 74 75 u_int cpuwatch_discover(void); 76 void cpuwatch_free(cpu_watchpoint_t *); 77 cpu_watchpoint_t *cpuwatch_alloc(void); 78 void cpuwatch_set_all(void); 79 void cpuwatch_clr_all(void); 80 void cpuwatch_set(cpu_watchpoint_t *); 81 void cpuwatch_clr(cpu_watchpoint_t *); 82 83 struct cpu_info { 84 struct cpu_data ci_data; /* MI per-cpu data */ 85 struct cpu_info *ci_next; /* Next CPU in list */ 86 struct cpu_softc *ci_softc; /* chip-dependent hook */ 87 device_t ci_dev; /* owning device */ 88 cpuid_t ci_cpuid; /* Machine-level identifier */ 89 u_long ci_cctr_freq; /* cycle counter frequency */ 90 u_long ci_cpu_freq; /* CPU frequency */ 91 u_long ci_cycles_per_hz; /* CPU freq / hz */ 92 u_long ci_divisor_delay; /* for delay/DELAY */ 93 u_long ci_divisor_recip; /* unused, for obsolete microtime(9) */ 94 struct lwp *ci_curlwp; /* currently running lwp */ 95 #ifndef NOFPU 96 struct lwp *ci_fpcurlwp; /* the current FPU owner */ 97 #endif 98 volatile int ci_want_resched; /* user preemption pending */ 99 int ci_mtx_count; /* negative count of held mutexes */ 100 int ci_mtx_oldspl; /* saved SPL value */ 101 int ci_idepth; /* hardware interrupt depth */ 102 int ci_cpl; /* current [interrupt] priority level */ 103 uint32_t ci_next_cp0_clk_intr; /* for hard clock intr scheduling */ 104 struct evcnt ci_ev_count_compare; /* hard clock intr counter */ 105 struct evcnt ci_ev_count_compare_missed; /* hard clock miss counter */ 106 struct lwp *ci_softlwps[SOFTINT_COUNT]; 107 volatile u_int ci_softints; 108 struct evcnt ci_ev_fpu_loads; /* fpu load counter */ 109 struct evcnt ci_ev_fpu_saves; /* fpu save counter */ 110 struct evcnt ci_ev_tlbmisses; 111 112 /* 113 * Per-cpu pmap information 114 */ 115 int ci_tlb_slot; /* reserved tlb entry for cpu_info */ 116 u_int ci_pmap_asid_cur; /* current ASID */ 117 struct pmap_tlb_info *ci_tlb_info; /* tlb information for this cpu */ 118 union segtab *ci_pmap_seg0tab; 119 #ifdef _LP64 120 union segtab *ci_pmap_segtab; 121 #else 122 vaddr_t ci_pmap_srcbase; /* starting VA of ephemeral src space */ 123 vaddr_t ci_pmap_dstbase; /* starting VA of ephemeral dst space */ 124 #endif 125 126 u_int ci_cpuwatch_count; /* number of watchpoints on this CPU */ 127 cpu_watchpoint_t ci_cpuwatch_tab[CPUWATCH_MAX]; 128 129 #ifdef MULTIPROCESSOR 130 volatile u_long ci_flags; 131 volatile uint64_t ci_request_ipis; 132 /* bitmask of IPIs requested */ 133 /* use on chips where hw cannot pass tag */ 134 uint64_t ci_active_ipis; /* bitmask of IPIs being serviced */ 135 uint32_t ci_ksp_tlb_slot; /* tlb entry for kernel stack */ 136 void *ci_fpsave_si; /* FP sync softint handler */ 137 struct evcnt ci_evcnt_all_ipis; /* aggregated IPI counter */ 138 struct evcnt ci_evcnt_per_ipi[NIPIS]; /* individual IPI counters*/ 139 struct evcnt ci_evcnt_synci_activate_rqst; 140 struct evcnt ci_evcnt_synci_onproc_rqst; 141 struct evcnt ci_evcnt_synci_deferred_rqst; 142 struct evcnt ci_evcnt_synci_ipi_rqst; 143 144 #define CPUF_PRIMARY 0x01 /* CPU is primary CPU */ 145 #define CPUF_PRESENT 0x02 /* CPU is present */ 146 #define CPUF_RUNNING 0x04 /* CPU is running */ 147 #define CPUF_PAUSED 0x08 /* CPU is paused */ 148 #define CPUF_FPUSAVE 0x10 /* CPU is currently in fpusave_cpu() */ 149 #define CPUF_USERPMAP 0x20 /* CPU has a user pmap activated */ 150 #endif 151 152 }; 153 154 #define CPU_INFO_ITERATOR int 155 #define CPU_INFO_FOREACH(cii, ci) \ 156 (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next 157 158 #endif /* !_LOCORE */ 159 #endif /* _KERNEL */ 160 161 /* 162 * CTL_MACHDEP definitions. 163 */ 164 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 165 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 166 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 167 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 168 169 /* 170 * Platform can override, but note this breaks userland compatibility 171 * with other mips platforms. 172 */ 173 #ifndef CPU_MAXID 174 #define CPU_MAXID 5 /* number of valid machdep ids */ 175 #endif 176 177 #ifdef _KERNEL 178 #if defined(_MODULAR) || defined(_LKM) || defined(_STANDALONE) 179 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 180 #define MIPS1 1 181 #define MIPS3 1 182 #define MIPS4 1 183 #define MIPS32 1 184 #define MIPS32R2 1 185 #define MIPS64 1 186 #define MIPS64R2 1 187 #define MIPS64_RMIXL 1 188 #define MIPS64R2_RMIXL 1 189 #endif 190 191 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) == 0 192 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32, MIPS32R2, MIPS64, MIPS64R2, MIPS64_RMIXL, or MIPS64R2_RMIXL must be specified 193 #endif 194 195 /* Shortcut for MIPS3 or above defined */ 196 #if defined(MIPS3) || defined(MIPS4) \ 197 || defined(MIPS32) || defined(MIPS32R2) \ 198 || defined(MIPS64) || defined(MIPS64R2) \ 199 || defined(MIPS64_RMIXL) || defined(MIPS64R2_RMIXL) 200 201 #define MIPS3_PLUS 1 202 #define __HAVE_CPU_COUNTER 203 #else 204 #undef MIPS3_PLUS 205 #endif 206 207 /* 208 * Macros to find the CPU architecture we're on at run-time, 209 * or if possible, at compile-time. 210 */ 211 212 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 213 #define CPU_ARCH_MIPS1 (1 << 0) 214 #define CPU_ARCH_MIPS2 (1 << 1) 215 #define CPU_ARCH_MIPS3 (1 << 2) 216 #define CPU_ARCH_MIPS4 (1 << 3) 217 #define CPU_ARCH_MIPS5 (1 << 4) 218 #define CPU_ARCH_MIPS32 (1 << 5) 219 #define CPU_ARCH_MIPS64 (1 << 6) 220 #define CPU_ARCH_MIPS32R2 (1 << 7) 221 #define CPU_ARCH_MIPS64R2 (1 << 8) 222 223 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 224 #define MIPS_CURLWP $24 225 #define MIPS_CURLWP_QUOTED "$24" 226 #define MIPS_CURLWP_LABEL _L_T8 227 #define MIPS_CURLWP_REG _R_T8 228 #define TF_MIPS_CURLWP(x) TF_REG_T8(x) 229 230 #ifndef _LOCORE 231 232 extern struct cpu_info cpu_info_store; 233 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 234 235 #define curlwp mips_curlwp 236 #define curcpu() (curlwp->l_cpu) 237 #define curpcb ((struct pcb *)lwp_getpcb(curlwp)) 238 #ifdef MULTIPROCESSOR 239 #define cpu_number() (curcpu()->ci_index) 240 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 241 #else 242 #define cpu_number() (0) 243 #define CPU_IS_PRIMARY(ci) (true) 244 #endif 245 246 /* XXX simonb 247 * Should the following be in a cpu_info type structure? 248 * And how many of these are per-cpu vs. per-system? (Ie, 249 * we can assume that all cpus have the same mmu-type, but 250 * maybe not that all cpus run at the same clock speed. 251 * Some SGI's apparently support R12k and R14k in the same 252 * box.) 253 */ 254 struct mips_options { 255 const struct pridtab *mips_cpu; 256 257 u_int mips_cpu_arch; 258 u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */ 259 u_int mips_cpu_flags; 260 u_int mips_num_tlb_entries; 261 mips_prid_t mips_cpu_id; 262 mips_prid_t mips_fpu_id; 263 bool mips_has_r4k_mmu; 264 bool mips_has_llsc; 265 u_int mips3_pg_shift; 266 u_int mips3_pg_cached; 267 #ifdef MIPS3_PLUS 268 #ifdef _LP64 269 uint64_t mips3_xkphys_cached; 270 #endif 271 uint64_t mips3_tlb_vpn_mask; 272 uint64_t mips3_tlb_pfn_mask; 273 uint32_t mips3_tlb_pg_mask; 274 #endif 275 }; 276 extern struct mips_options mips_options; 277 278 #define CPU_MIPS_R4K_MMU 0x0001 279 #define CPU_MIPS_NO_LLSC 0x0002 280 #define CPU_MIPS_CAUSE_IV 0x0004 281 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 282 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 283 #define CPU_MIPS_CACHED_CCA_SHIFT 4 284 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 285 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 286 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 287 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 288 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 289 #define CPU_MIPS_NO_LLADDR 0x1000 290 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 291 #define MIPS_NOT_SUPP 0x8000 292 293 #endif /* !_LOCORE */ 294 295 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) == 1) || defined(_LOCORE) 296 297 #if defined(MIPS1) 298 299 # define CPUISMIPS3 0 300 # define CPUIS64BITS 0 301 # define CPUISMIPS32 0 302 # define CPUISMIPS32R2 0 303 # define CPUISMIPS64 0 304 # define CPUISMIPS64R2 0 305 # define CPUISMIPSNN 0 306 # define MIPS_HAS_R4K_MMU 0 307 # define MIPS_HAS_CLOCK 0 308 # define MIPS_HAS_LLSC 0 309 # define MIPS_HAS_LLADDR 0 310 311 #elif defined(MIPS3) || defined(MIPS4) 312 313 # define CPUISMIPS3 1 314 # define CPUIS64BITS 1 315 # define CPUISMIPS32 0 316 # define CPUISMIPS32R2 0 317 # define CPUISMIPS64 0 318 # define CPUISMIPS64R2 0 319 # define CPUISMIPSNN 0 320 # define MIPS_HAS_R4K_MMU 1 321 # define MIPS_HAS_CLOCK 1 322 # if defined(_LOCORE) 323 # if !defined(MIPS3_4100) 324 # define MIPS_HAS_LLSC 1 325 # else 326 # define MIPS_HAS_LLSC 0 327 # endif 328 # else /* _LOCORE */ 329 # define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 330 # endif /* _LOCORE */ 331 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 332 333 #elif defined(MIPS32) 334 335 # define CPUISMIPS3 1 336 # define CPUIS64BITS 0 337 # define CPUISMIPS32 1 338 # define CPUISMIPS32R2 0 339 # define CPUISMIPS64 0 340 # define CPUISMIPS64R2 0 341 # define CPUISMIPSNN 1 342 # define MIPS_HAS_R4K_MMU 1 343 # define MIPS_HAS_CLOCK 1 344 # define MIPS_HAS_LLSC 1 345 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 346 347 #elif defined(MIPS32R2) 348 349 # define CPUISMIPS3 1 350 # define CPUIS64BITS 0 351 # define CPUISMIPS32 0 352 # define CPUISMIPS32R2 1 353 # define CPUISMIPS64 0 354 # define CPUISMIPS64R2 0 355 # define CPUISMIPSNN 1 356 # define MIPS_HAS_R4K_MMU 1 357 # define MIPS_HAS_CLOCK 1 358 # define MIPS_HAS_LLSC 1 359 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 360 361 #elif defined(MIPS64) || defined(MIPS64_RMIXL) 362 363 # define CPUISMIPS3 1 364 # define CPUIS64BITS 1 365 # define CPUISMIPS32 0 366 # define CPUISMIPS32R2 0 367 # define CPUISMIPS64 1 368 # define CPUISMIPS64R2 0 369 # define CPUISMIPSNN 1 370 # define MIPS_HAS_R4K_MMU 1 371 # define MIPS_HAS_CLOCK 1 372 # define MIPS_HAS_LLSC 1 373 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 374 375 #elif defined(MIPS64R2) || defined(MIPS64R2_RMIXL) 376 377 # define CPUISMIPS3 1 378 # define CPUIS64BITS 1 379 # define CPUISMIPS32 0 380 # define CPUISMIPS32R2 0 381 # define CPUISMIPS64 0 382 # define CPUISMIPS64R2 1 383 # define CPUISMIPSNN 1 384 # define MIPS_HAS_R4K_MMU 1 385 # define MIPS_HAS_CLOCK 1 386 # define MIPS_HAS_LLSC 1 387 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 388 389 #endif 390 391 #else /* run-time test */ 392 393 #ifndef _LOCORE 394 395 #define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu) 396 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 397 #define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 398 399 /* This test is ... rather bogus */ 400 #define CPUISMIPS3 ((mips_options.mips_cpu_arch & \ 401 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 402 403 /* And these aren't much better while the previous test exists as is... */ 404 #define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0) 405 #define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0) 406 #define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0) 407 #define CPUISMIPS32R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32R2) != 0) 408 #define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0) 409 #define CPUISMIPS64R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64R2) != 0) 410 #define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS32R2 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 411 #define CPUIS64BITS ((mips_options.mips_cpu_arch & \ 412 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 413 414 #define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) 415 416 #else /* !_LOCORE */ 417 418 #define MIPS_HAS_LLSC 0 419 420 #endif /* !_LOCORE */ 421 422 #endif /* run-time test */ 423 424 #ifndef _LOCORE 425 426 /* 427 * definitions of cpu-dependent requirements 428 * referenced in generic code 429 */ 430 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 431 432 /* 433 * Send an inter-processor interupt to each other CPU (excludes curcpu()) 434 */ 435 void cpu_broadcast_ipi(int); 436 437 /* 438 * Send an inter-processor interupt to CPUs in cpuset (excludes curcpu()) 439 */ 440 void cpu_multicast_ipi(__cpuset_t, int); 441 442 /* 443 * Send an inter-processor interupt to another CPU. 444 */ 445 int cpu_send_ipi(struct cpu_info *, int); 446 447 /* 448 * cpu_intr(ppl, pc, status); (most state needed by clockframe) 449 */ 450 void cpu_intr(int, vaddr_t, uint32_t); 451 452 /* 453 * Arguments to hardclock and gatherstats encapsulate the previous 454 * machine state in an opaque clockframe. 455 */ 456 struct clockframe { 457 vaddr_t pc; /* program counter at time of interrupt */ 458 uint32_t sr; /* status register at time of interrupt */ 459 bool intr; /* interrupted a interrupt */ 460 }; 461 462 /* 463 * A port must provde CLKF_USERMODE() for use in machine-independent code. 464 * These differ on r4000 and r3000 systems; provide them in the 465 * port-dependent file that includes this one, using the macros below. 466 */ 467 468 /* mips1 versions */ 469 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 470 471 /* mips3 versions */ 472 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 473 474 #define CLKF_PC(framep) ((framep)->pc) 475 #define CLKF_INTR(framep) ((framep)->intr) 476 477 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 478 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 479 #endif 480 481 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 482 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 483 #endif 484 485 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 486 #define CLKF_USERMODE(framep) \ 487 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 488 #endif 489 490 /* 491 * Misc prototypes and variable declarations. 492 */ 493 #define LWP_PC(l) cpu_lwp_pc(l) 494 495 struct proc; 496 struct lwp; 497 struct pcb; 498 struct reg; 499 500 /* 501 * Preempt the current process if in interrupt from user mode, 502 * or after the current trap/syscall if in system mode. 503 */ 504 void cpu_need_resched(struct cpu_info *, int); 505 /* 506 * Notify the current lwp (l) that it has a signal pending, 507 * process as soon as possible. 508 */ 509 void cpu_signotify(struct lwp *); 510 511 /* 512 * Give a profiling tick to the current process when the user profiling 513 * buffer pages are invalid. On the MIPS, request an ast to send us 514 * through trap, marking the proc as needing a profiling tick. 515 */ 516 void cpu_need_proftick(struct lwp *); 517 void cpu_set_curpri(int); 518 519 extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */ 520 521 struct cpu_info * 522 cpu_info_alloc(struct pmap_tlb_info *, cpuid_t, cpuid_t, cpuid_t, 523 cpuid_t); 524 void cpu_attach_common(device_t, struct cpu_info *); 525 void cpu_startup_common(void); 526 #ifdef _LP64 527 void cpu_vmspace_exec(struct lwp *, vaddr_t, vaddr_t); 528 #endif 529 530 #ifdef MULTIPROCESSOR 531 void cpu_hatch(struct cpu_info *ci); 532 void cpu_trampoline(void); 533 void cpu_boot_secondary_processors(void); 534 void cpu_halt(void); 535 void cpu_halt_others(void); 536 void cpu_pause(struct reg *); 537 void cpu_pause_others(void); 538 void cpu_resume(int); 539 void cpu_resume_others(void); 540 int cpu_is_paused(int); 541 void cpu_debug_dump(void); 542 543 extern volatile __cpuset_t cpus_running; 544 extern volatile __cpuset_t cpus_hatched; 545 extern volatile __cpuset_t cpus_paused; 546 extern volatile __cpuset_t cpus_resumed; 547 extern volatile __cpuset_t cpus_halted; 548 #endif 549 550 /* copy.S */ 551 int8_t ufetch_int8(void *); 552 int16_t ufetch_int16(void *); 553 int32_t ufetch_int32(void *); 554 uint8_t ufetch_uint8(void *); 555 uint16_t ufetch_uint16(void *); 556 uint32_t ufetch_uint32(void *); 557 int8_t ufetch_int8_intrsafe(void *); 558 int16_t ufetch_int16_intrsafe(void *); 559 int32_t ufetch_int32_intrsafe(void *); 560 uint8_t ufetch_uint8_intrsafe(void *); 561 uint16_t ufetch_uint16_intrsafe(void *); 562 uint32_t ufetch_uint32_intrsafe(void *); 563 #ifdef _LP64 564 int64_t ufetch_int64(void *); 565 uint64_t ufetch_uint64(void *); 566 int64_t ufetch_int64_intrsafe(void *); 567 uint64_t ufetch_uint64_intrsafe(void *); 568 #endif 569 char ufetch_char(void *); 570 short ufetch_short(void *); 571 int ufetch_int(void *); 572 long ufetch_long(void *); 573 char ufetch_char_intrsafe(void *); 574 short ufetch_short_intrsafe(void *); 575 int ufetch_int_intrsafe(void *); 576 long ufetch_long_intrsafe(void *); 577 578 u_char ufetch_uchar(void *); 579 u_short ufetch_ushort(void *); 580 u_int ufetch_uint(void *); 581 u_long ufetch_ulong(void *); 582 u_char ufetch_uchar_intrsafe(void *); 583 u_short ufetch_ushort_intrsafe(void *); 584 u_int ufetch_uint_intrsafe(void *); 585 u_long ufetch_ulong_intrsafe(void *); 586 void *ufetch_ptr(void *); 587 588 int ustore_int8(void *, int8_t); 589 int ustore_int16(void *, int16_t); 590 int ustore_int32(void *, int32_t); 591 int ustore_uint8(void *, uint8_t); 592 int ustore_uint16(void *, uint16_t); 593 int ustore_uint32(void *, uint32_t); 594 int ustore_int8_intrsafe(void *, int8_t); 595 int ustore_int16_intrsafe(void *, int16_t); 596 int ustore_int32_intrsafe(void *, int32_t); 597 int ustore_uint8_intrsafe(void *, uint8_t); 598 int ustore_uint16_intrsafe(void *, uint16_t); 599 int ustore_uint32_intrsafe(void *, uint32_t); 600 #ifdef _LP64 601 int ustore_int64(void *, int64_t); 602 int ustore_uint64(void *, uint64_t); 603 int ustore_int64_intrsafe(void *, int64_t); 604 int ustore_uint64_intrsafe(void *, uint64_t); 605 #endif 606 int ustore_char(void *, char); 607 int ustore_char_intrsafe(void *, char); 608 int ustore_short(void *, short); 609 int ustore_short_intrsafe(void *, short); 610 int ustore_int(void *, int); 611 int ustore_int_intrsafe(void *, int); 612 int ustore_long(void *, long); 613 int ustore_long_intrsafe(void *, long); 614 int ustore_uchar(void *, u_char); 615 int ustore_uchar_intrsafe(void *, u_char); 616 int ustore_ushort(void *, u_short); 617 int ustore_ushort_intrsafe(void *, u_short); 618 int ustore_uint(void *, u_int); 619 int ustore_uint_intrsafe(void *, u_int); 620 int ustore_ulong(void *, u_long); 621 int ustore_ulong_intrsafe(void *, u_long); 622 int ustore_ptr(void *, void *); 623 int ustore_ptr_intrsafe(void *, void *); 624 625 int ustore_uint32_isync(void *, uint32_t); 626 627 /* trap.c */ 628 void netintr(void); 629 int kdbpeek(vaddr_t); 630 631 /* mips_fpu.c */ 632 void fpu_init(void); 633 void fpu_discard(void); 634 void fpu_load(void); 635 void fpu_save(void); 636 void fpu_save_lwp(struct lwp *); 637 void fpusave_cpu(struct cpu_info *); 638 639 /* mips_machdep.c */ 640 void dumpsys(void); 641 int savectx(struct pcb *); 642 void cpu_identify(device_t); 643 644 /* locore*.S */ 645 int badaddr(void *, size_t); 646 int badaddr64(uint64_t, size_t); 647 648 /* vm_machdep.c */ 649 void cpu_proc_fork(struct proc *, struct proc *); 650 vaddr_t cpu_lwp_pc(struct lwp *); 651 void cpu_uarea_remap(struct lwp *); 652 653 #endif /* ! _LOCORE */ 654 #endif /* _KERNEL */ 655 #endif /* _CPU_H_ */ 656
Indexes created Sun Oct 12 20:09:57 GMT 2025