Home | History | Annotate | Line # | Download | only in include
cpu.h revision 1.90.16.38
      1 /*	cpu.h,v 1.90.16.36 2011/04/29 08:26:20 matt Exp	*/
      2 
      3 /*-
      4  * Copyright (c) 1992, 1993
      5  *	The Regents of the University of California.  All rights reserved.
      6  *
      7  * This code is derived from software contributed to Berkeley by
      8  * Ralph Campbell and Rick Macklem.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. Neither the name of the University nor the names of its contributors
     19  *    may be used to endorse or promote products derived from this software
     20  *    without specific prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  * SUCH DAMAGE.
     33  *
     34  *	@(#)cpu.h	8.4 (Berkeley) 1/4/94
     35  */
     36 
     37 #ifndef _CPU_H_
     38 #define _CPU_H_
     39 
     40 #include <mips/cpuregs.h>
     41 
     42 /*
     43  * Exported definitions unique to NetBSD/mips cpu support.
     44  */
     45 
     46 #ifdef _KERNEL
     47 
     48 #if defined(_KERNEL_OPT)
     49 #include "opt_cputype.h"
     50 #include "opt_lockdebug.h"
     51 #include "opt_multiprocessor.h"
     52 #endif
     53 
     54 #ifndef _LOCORE
     55 #include <sys/cpu_data.h>
     56 #include <sys/device.h>
     57 #include <sys/evcnt.h>
     58 
     59 typedef struct cpu_watchpoint {
     60 	register_t	cw_addr;
     61 	register_t	cw_mask;
     62 	uint32_t	cw_asid;
     63 	uint32_t	cw_mode;
     64 } cpu_watchpoint_t;
     65 /* (abstract) mode bits */
     66 #define CPUWATCH_WRITE	__BIT(0)
     67 #define CPUWATCH_READ	__BIT(1)
     68 #define CPUWATCH_EXEC	__BIT(2)
     69 #define CPUWATCH_MASK	__BIT(3)
     70 #define CPUWATCH_ASID	__BIT(4)
     71 #define CPUWATCH_RWX	(CPUWATCH_EXEC|CPUWATCH_READ|CPUWATCH_WRITE)
     72 
     73 #define CPUWATCH_MAX	8	/* max possible number of watchpoints */
     74 
     75 u_int		  cpuwatch_discover(void);
     76 void		  cpuwatch_free(cpu_watchpoint_t *);
     77 cpu_watchpoint_t *cpuwatch_alloc(void);
     78 void		  cpuwatch_set_all(void);
     79 void		  cpuwatch_clr_all(void);
     80 void		  cpuwatch_set(cpu_watchpoint_t *);
     81 void		  cpuwatch_clr(cpu_watchpoint_t *);
     82 
     83 struct cpu_info {
     84 	struct cpu_data ci_data;	/* MI per-cpu data */
     85 	struct cpu_info *ci_next;	/* Next CPU in list */
     86 	struct cpu_softc *ci_softc;	/* chip-dependent hook */
     87 	device_t ci_dev;		/* owning device */
     88 	cpuid_t ci_cpuid;		/* Machine-level identifier */
     89 	u_long ci_cctr_freq;		/* cycle counter frequency */
     90 	u_long ci_cpu_freq;		/* CPU frequency */
     91 	u_long ci_cycles_per_hz;	/* CPU freq / hz */
     92 	u_long ci_divisor_delay;	/* for delay/DELAY */
     93 	u_long ci_divisor_recip;	/* unused, for obsolete microtime(9) */
     94 	struct lwp *ci_curlwp;		/* currently running lwp */
     95 #ifndef NOFPU
     96 	struct lwp *ci_fpcurlwp;	/* the current FPU owner */
     97 #endif
     98 	volatile int ci_want_resched;	/* user preemption pending */
     99 	int ci_mtx_count;		/* negative count of held mutexes */
    100 	int ci_mtx_oldspl;		/* saved SPL value */
    101 	int ci_idepth;			/* hardware interrupt depth */
    102 	int ci_cpl;			/* current [interrupt] priority level */
    103 	uint32_t ci_next_cp0_clk_intr;	/* for hard clock intr scheduling */
    104 	struct evcnt ci_ev_count_compare;		/* hard clock intr counter */
    105 	struct evcnt ci_ev_count_compare_missed;	/* hard clock miss counter */
    106 	struct lwp *ci_softlwps[SOFTINT_COUNT];
    107 	volatile u_int ci_softints;
    108 	struct evcnt ci_ev_fpu_loads;	/* fpu load counter */
    109 	struct evcnt ci_ev_fpu_saves;	/* fpu save counter */
    110 	struct evcnt ci_ev_kern_tlbmisses;
    111 	struct evcnt ci_ev_user_tlbmisses;
    112 	struct evcnt ci_ev_tlblocked;
    113 
    114 	/*
    115 	 * Per-cpu pmap information
    116 	 */
    117 	int ci_tlb_slot;		/* reserved tlb entry for cpu_info */
    118 	u_int ci_pmap_asid_cur;		/* current ASID */
    119 	struct pmap_tlb_info *ci_tlb_info; /* tlb information for this cpu */
    120 	union segtab *ci_pmap_seg0tab;
    121 #ifdef _LP64
    122 	union segtab *ci_pmap_segtab;
    123 #else
    124 	vaddr_t ci_pmap_srcbase;	/* starting VA of ephemeral src space */
    125 	vaddr_t ci_pmap_dstbase;	/* starting VA of ephemeral dst space */
    126 #endif
    127 
    128 	u_int ci_cpuwatch_count;	/* number of watchpoints on this CPU */
    129 	cpu_watchpoint_t ci_cpuwatch_tab[CPUWATCH_MAX];
    130 
    131 #ifdef MULTIPROCESSOR
    132 	volatile u_long ci_flags;
    133 	volatile uint64_t ci_request_ipis;
    134 					/* bitmask of IPIs requested */
    135 					/*  use on chips where hw cannot pass tag */
    136 	uint64_t ci_active_ipis;	/* bitmask of IPIs being serviced */
    137 	uint32_t ci_ksp_tlb_slot;	/* tlb entry for kernel stack */
    138 	void *ci_fpsave_si;		/* FP sync softint handler */
    139 	struct evcnt ci_evcnt_all_ipis;	/* aggregated IPI counter */
    140 	struct evcnt ci_evcnt_per_ipi[NIPIS];	/* individual IPI counters*/
    141 	struct evcnt ci_evcnt_synci_activate_rqst;
    142 	struct evcnt ci_evcnt_synci_onproc_rqst;
    143 	struct evcnt ci_evcnt_synci_deferred_rqst;
    144 	struct evcnt ci_evcnt_synci_ipi_rqst;
    145 
    146 #define	CPUF_PRIMARY	0x01		/* CPU is primary CPU */
    147 #define	CPUF_PRESENT	0x02		/* CPU is present */
    148 #define	CPUF_RUNNING	0x04		/* CPU is running */
    149 #define	CPUF_PAUSED	0x08		/* CPU is paused */
    150 #define	CPUF_FPUSAVE	0x10		/* CPU is currently in fpusave_cpu() */
    151 #define	CPUF_USERPMAP	0x20		/* CPU has a user pmap activated */
    152 #endif
    153 
    154 };
    155 
    156 #define	CPU_INFO_ITERATOR		int
    157 #define	CPU_INFO_FOREACH(cii, ci)	\
    158     (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next
    159 
    160 #endif /* !_LOCORE */
    161 #endif /* _KERNEL */
    162 
    163 /*
    164  * CTL_MACHDEP definitions.
    165  */
    166 #define CPU_CONSDEV		1	/* dev_t: console terminal device */
    167 #define CPU_BOOTED_KERNEL	2	/* string: booted kernel name */
    168 #define CPU_ROOT_DEVICE		3	/* string: root device name */
    169 #define CPU_LLSC		4	/* OS/CPU supports LL/SC instruction */
    170 
    171 /*
    172  * Platform can override, but note this breaks userland compatibility
    173  * with other mips platforms.
    174  */
    175 #ifndef CPU_MAXID
    176 #define CPU_MAXID		5	/* number of valid machdep ids */
    177 #endif
    178 
    179 #ifdef _KERNEL
    180 #if defined(_MODULAR) || defined(_LKM) || defined(_STANDALONE)
    181 /* Assume all CPU architectures are valid for LKM's and standlone progs */
    182 #define	MIPS1		1
    183 #define	MIPS3		1
    184 #define	MIPS4		1
    185 #define	MIPS32		1
    186 #define	MIPS32R2	1
    187 #define	MIPS64		1
    188 #define	MIPS64R2	1
    189 #define	MIPS64_RMIXL	1
    190 #define	MIPS64R2_RMIXL	1
    191 #endif
    192 
    193 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) == 0
    194 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32, MIPS32R2, MIPS64, MIPS64R2, MIPS64_RMIXL, or MIPS64R2_RMIXL must be specified
    195 #endif
    196 
    197 /* Shortcut for MIPS3 or above defined */
    198 #if defined(MIPS3) || defined(MIPS4) \
    199     || defined(MIPS32) || defined(MIPS32R2) \
    200     || defined(MIPS64) || defined(MIPS64R2) \
    201     || defined(MIPS64_RMIXL) || defined(MIPS64R2_RMIXL)
    202 
    203 #define	MIPS3_PLUS	1
    204 #define __HAVE_CPU_COUNTER
    205 #else
    206 #undef MIPS3_PLUS
    207 #endif
    208 
    209 /*
    210  * Macros to find the CPU architecture we're on at run-time,
    211  * or if possible, at compile-time.
    212  */
    213 
    214 #define	CPU_ARCH_MIPSx		0		/* XXX unknown */
    215 #define	CPU_ARCH_MIPS1		(1 << 0)
    216 #define	CPU_ARCH_MIPS2		(1 << 1)
    217 #define	CPU_ARCH_MIPS3		(1 << 2)
    218 #define	CPU_ARCH_MIPS4		(1 << 3)
    219 #define	CPU_ARCH_MIPS5		(1 << 4)
    220 #define	CPU_ARCH_MIPS32		(1 << 5)
    221 #define	CPU_ARCH_MIPS64		(1 << 6)
    222 #define	CPU_ARCH_MIPS32R2	(1 << 7)
    223 #define	CPU_ARCH_MIPS64R2	(1 << 8)
    224 
    225 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */
    226 #define MIPS_CURLWP             $24
    227 #define MIPS_CURLWP_QUOTED      "$24"
    228 #define MIPS_CURLWP_LABEL	_L_T8
    229 #define MIPS_CURLWP_REG		_R_T8
    230 #define TF_MIPS_CURLWP(x)	TF_REG_T8(x)
    231 
    232 #ifndef _LOCORE
    233 
    234 extern struct cpu_info cpu_info_store;
    235 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED);
    236 
    237 #define	curlwp			mips_curlwp
    238 #define	curcpu()		(curlwp->l_cpu)
    239 #define	curpcb			((struct pcb *)lwp_getpcb(curlwp))
    240 #ifdef MULTIPROCESSOR
    241 #define	cpu_number()		(curcpu()->ci_index)
    242 #define	CPU_IS_PRIMARY(ci)	((ci)->ci_flags & CPUF_PRIMARY)
    243 #else
    244 #define	cpu_number()		(0)
    245 #define	CPU_IS_PRIMARY(ci)	(true)
    246 #endif
    247 
    248 /* XXX simonb
    249  * Should the following be in a cpu_info type structure?
    250  * And how many of these are per-cpu vs. per-system?  (Ie,
    251  * we can assume that all cpus have the same mmu-type, but
    252  * maybe not that all cpus run at the same clock speed.
    253  * Some SGI's apparently support R12k and R14k in the same
    254  * box.)
    255  */
    256 struct mips_options {
    257 	const struct pridtab *mips_cpu;
    258 
    259 	u_int mips_cpu_arch;
    260 	u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */
    261 	u_int mips_cpu_flags;
    262 	u_int mips_num_tlb_entries;
    263 	mips_prid_t mips_cpu_id;
    264 	mips_prid_t mips_fpu_id;
    265 	bool mips_has_r4k_mmu;
    266 	bool mips_has_llsc;
    267 	u_int mips3_pg_shift;
    268 	u_int mips3_pg_cached;
    269 #ifdef MIPS3_PLUS
    270 #ifdef _LP64
    271 	uint64_t mips3_xkphys_cached;
    272 #endif
    273 	uint64_t mips3_tlb_vpn_mask;
    274 	uint64_t mips3_tlb_pfn_mask;
    275 	uint32_t mips3_tlb_pg_mask;
    276 #endif
    277 };
    278 extern struct mips_options mips_options;
    279 
    280 #define	CPU_MIPS_R4K_MMU		0x0001
    281 #define	CPU_MIPS_NO_LLSC		0x0002
    282 #define	CPU_MIPS_CAUSE_IV		0x0004
    283 #define	CPU_MIPS_HAVE_SPECIAL_CCA	0x0008	/* Defaults to '3' if not set. */
    284 #define	CPU_MIPS_CACHED_CCA_MASK	0x0070
    285 #define	CPU_MIPS_CACHED_CCA_SHIFT	 4
    286 #define	CPU_MIPS_DOUBLE_COUNT		0x0080	/* 1 cp0 count == 2 clock cycles */
    287 #define	CPU_MIPS_USE_WAIT		0x0100	/* Use "wait"-based cpu_idle() */
    288 #define	CPU_MIPS_NO_WAIT		0x0200	/* Inverse of previous, for mips32/64 */
    289 #define	CPU_MIPS_D_CACHE_COHERENT	0x0400	/* D-cache is fully coherent */
    290 #define	CPU_MIPS_I_D_CACHE_COHERENT	0x0800	/* I-cache funcs don't need to flush the D-cache */
    291 #define	CPU_MIPS_NO_LLADDR		0x1000
    292 #define	CPU_MIPS_HAVE_MxCR		0x2000	/* have mfcr, mtcr insns */
    293 #define	MIPS_NOT_SUPP			0x8000
    294 
    295 #endif	/* !_LOCORE */
    296 
    297 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) == 1) || defined(_LOCORE)
    298 
    299 #if defined(MIPS1)
    300 
    301 # define CPUISMIPS3		0
    302 # define CPUIS64BITS		0
    303 # define CPUISMIPS32		0
    304 # define CPUISMIPS32R2		0
    305 # define CPUISMIPS64		0
    306 # define CPUISMIPS64R2		0
    307 # define CPUISMIPSNN		0
    308 # define MIPS_HAS_R4K_MMU	0
    309 # define MIPS_HAS_CLOCK		0
    310 # define MIPS_HAS_LLSC		0
    311 # define MIPS_HAS_LLADDR	0
    312 
    313 #elif defined(MIPS3) || defined(MIPS4)
    314 
    315 # define CPUISMIPS3		1
    316 # define CPUIS64BITS		1
    317 # define CPUISMIPS32		0
    318 # define CPUISMIPS32R2		0
    319 # define CPUISMIPS64		0
    320 # define CPUISMIPS64R2		0
    321 # define CPUISMIPSNN		0
    322 # define MIPS_HAS_R4K_MMU	1
    323 # define MIPS_HAS_CLOCK		1
    324 # if defined(_LOCORE)
    325 #  if !defined(MIPS3_4100)
    326 #   define MIPS_HAS_LLSC	1
    327 #  else
    328 #   define MIPS_HAS_LLSC	0
    329 #  endif
    330 # else	/* _LOCORE */
    331 #  define MIPS_HAS_LLSC		(mips_options.mips_has_llsc)
    332 # endif	/* _LOCORE */
    333 # define MIPS_HAS_LLADDR	((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
    334 
    335 #elif defined(MIPS32)
    336 
    337 # define CPUISMIPS3		1
    338 # define CPUIS64BITS		0
    339 # define CPUISMIPS32		1
    340 # define CPUISMIPS32R2		0
    341 # define CPUISMIPS64		0
    342 # define CPUISMIPS64R2		0
    343 # define CPUISMIPSNN		1
    344 # define MIPS_HAS_R4K_MMU	1
    345 # define MIPS_HAS_CLOCK		1
    346 # define MIPS_HAS_LLSC		1
    347 # define MIPS_HAS_LLADDR	((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
    348 
    349 #elif defined(MIPS32R2)
    350 
    351 # define CPUISMIPS3		1
    352 # define CPUIS64BITS		0
    353 # define CPUISMIPS32		0
    354 # define CPUISMIPS32R2		1
    355 # define CPUISMIPS64		0
    356 # define CPUISMIPS64R2		0
    357 # define CPUISMIPSNN		1
    358 # define MIPS_HAS_R4K_MMU	1
    359 # define MIPS_HAS_CLOCK		1
    360 # define MIPS_HAS_LLSC		1
    361 # define MIPS_HAS_LLADDR	((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
    362 
    363 #elif defined(MIPS64) || defined(MIPS64_RMIXL)
    364 
    365 # define CPUISMIPS3		1
    366 # define CPUIS64BITS		1
    367 # define CPUISMIPS32		0
    368 # define CPUISMIPS32R2		0
    369 # define CPUISMIPS64		1
    370 # define CPUISMIPS64R2		0
    371 # define CPUISMIPSNN		1
    372 # define MIPS_HAS_R4K_MMU	1
    373 # define MIPS_HAS_CLOCK		1
    374 # define MIPS_HAS_LLSC		1
    375 # define MIPS_HAS_LLADDR	((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
    376 
    377 #elif defined(MIPS64R2) || defined(MIPS64R2_RMIXL)
    378 
    379 # define CPUISMIPS3		1
    380 # define CPUIS64BITS		1
    381 # define CPUISMIPS32		0
    382 # define CPUISMIPS32R2		0
    383 # define CPUISMIPS64		0
    384 # define CPUISMIPS64R2		1
    385 # define CPUISMIPSNN		1
    386 # define MIPS_HAS_R4K_MMU	1
    387 # define MIPS_HAS_CLOCK		1
    388 # define MIPS_HAS_LLSC		1
    389 # define MIPS_HAS_LLADDR	((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
    390 
    391 #endif
    392 
    393 #else /* run-time test */
    394 
    395 #ifndef	_LOCORE
    396 
    397 #define	MIPS_HAS_R4K_MMU	(mips_options.mips_has_r4k_mmu)
    398 #define	MIPS_HAS_LLSC		(mips_options.mips_has_llsc)
    399 #define	MIPS_HAS_LLADDR		((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
    400 
    401 /* This test is ... rather bogus */
    402 #define	CPUISMIPS3	((mips_options.mips_cpu_arch & \
    403 	(CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0)
    404 
    405 /* And these aren't much better while the previous test exists as is... */
    406 #define	CPUISMIPS4	((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0)
    407 #define	CPUISMIPS5	((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0)
    408 #define	CPUISMIPS32	((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0)
    409 #define	CPUISMIPS32R2	((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32R2) != 0)
    410 #define	CPUISMIPS64	((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0)
    411 #define	CPUISMIPS64R2	((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64R2) != 0)
    412 #define	CPUISMIPSNN	((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS32R2 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0)
    413 #define	CPUIS64BITS	((mips_options.mips_cpu_arch & \
    414 	(CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0)
    415 
    416 #define	MIPS_HAS_CLOCK	(mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3)
    417 
    418 #else	/* !_LOCORE */
    419 
    420 #define	MIPS_HAS_LLSC	0
    421 
    422 #endif	/* !_LOCORE */
    423 
    424 #endif /* run-time test */
    425 
    426 #ifndef	_LOCORE
    427 
    428 /*
    429  * definitions of cpu-dependent requirements
    430  * referenced in generic code
    431  */
    432 #define	cpu_swapout(p)			panic("cpu_swapout: can't get here");
    433 
    434 /*
    435  * Send an inter-processor interupt to each other CPU (excludes curcpu())
    436  */
    437 void cpu_broadcast_ipi(int);
    438 
    439 /*
    440  * Send an inter-processor interupt to CPUs in cpuset (excludes curcpu())
    441  */
    442 void cpu_multicast_ipi(__cpuset_t, int);
    443 
    444 /*
    445  * Send an inter-processor interupt to another CPU.
    446  */
    447 int cpu_send_ipi(struct cpu_info *, int);
    448 
    449 /*
    450  * cpu_intr(ppl, pc, status);  (most state needed by clockframe)
    451  */
    452 void cpu_intr(int, vaddr_t, uint32_t);
    453 
    454 /*
    455  * Arguments to hardclock and gatherstats encapsulate the previous
    456  * machine state in an opaque clockframe.
    457  */
    458 struct clockframe {
    459 	vaddr_t		pc;	/* program counter at time of interrupt */
    460 	uint32_t	sr;	/* status register at time of interrupt */
    461 	bool		intr;	/* interrupted a interrupt */
    462 };
    463 
    464 /*
    465  * A port must provde CLKF_USERMODE() for use in machine-independent code.
    466  * These differ on r4000 and r3000 systems; provide them in the
    467  * port-dependent file that includes this one, using the macros below.
    468  */
    469 
    470 /* mips1 versions */
    471 #define	MIPS1_CLKF_USERMODE(framep)	((framep)->sr & MIPS_SR_KU_PREV)
    472 
    473 /* mips3 versions */
    474 #define	MIPS3_CLKF_USERMODE(framep)	((framep)->sr & MIPS_SR_KSU_USER)
    475 
    476 #define	CLKF_PC(framep)		((framep)->pc)
    477 #define	CLKF_INTR(framep)	((framep)->intr)
    478 
    479 #if defined(MIPS3_PLUS) && !defined(MIPS1)		/* XXX bogus! */
    480 #define	CLKF_USERMODE(framep)	MIPS3_CLKF_USERMODE(framep)
    481 #endif
    482 
    483 #if !defined(MIPS3_PLUS) && defined(MIPS1)		/* XXX bogus! */
    484 #define	CLKF_USERMODE(framep)	MIPS1_CLKF_USERMODE(framep)
    485 #endif
    486 
    487 #if defined(MIPS3_PLUS) && defined(MIPS1)		/* XXX bogus! */
    488 #define CLKF_USERMODE(framep) \
    489     ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep):  MIPS1_CLKF_USERMODE(framep))
    490 #endif
    491 
    492 /*
    493  * Misc prototypes and variable declarations.
    494  */
    495 #define	LWP_PC(l)	cpu_lwp_pc(l)
    496 
    497 struct proc;
    498 struct lwp;
    499 struct pcb;
    500 struct reg;
    501 
    502 /*
    503  * Preempt the current process if in interrupt from user mode,
    504  * or after the current trap/syscall if in system mode.
    505  */
    506 void	cpu_need_resched(struct cpu_info *, int);
    507 /*
    508  * Notify the current lwp (l) that it has a signal pending,
    509  * process as soon as possible.
    510  */
    511 void	cpu_signotify(struct lwp *);
    512 
    513 /*
    514  * Give a profiling tick to the current process when the user profiling
    515  * buffer pages are invalid.  On the MIPS, request an ast to send us
    516  * through trap, marking the proc as needing a profiling tick.
    517  */
    518 void	cpu_need_proftick(struct lwp *);
    519 void	cpu_set_curpri(int);
    520 
    521 extern int mips_poolpage_vmfreelist;	/* freelist to allocate poolpages */
    522 
    523 struct cpu_info *
    524 	cpu_info_alloc(struct pmap_tlb_info *, cpuid_t, cpuid_t, cpuid_t,
    525 	    cpuid_t);
    526 void	cpu_attach_common(device_t, struct cpu_info *);
    527 void	cpu_startup_common(void);
    528 #ifdef _LP64
    529 void	cpu_vmspace_exec(struct lwp *, vaddr_t, vaddr_t);
    530 #endif
    531 
    532 #ifdef MULTIPROCESSOR
    533 void	cpu_hatch(struct cpu_info *ci);
    534 void	cpu_trampoline(void);
    535 void	cpu_boot_secondary_processors(void);
    536 void	cpu_halt(void);
    537 void	cpu_halt_others(void);
    538 void	cpu_pause(struct reg *);
    539 void	cpu_pause_others(void);
    540 void	cpu_resume(int);
    541 void	cpu_resume_others(void);
    542 int	cpu_is_paused(int);
    543 void	cpu_debug_dump(void);
    544 
    545 extern volatile __cpuset_t cpus_running;
    546 extern volatile __cpuset_t cpus_hatched;
    547 extern volatile __cpuset_t cpus_paused;
    548 extern volatile __cpuset_t cpus_resumed;
    549 extern volatile __cpuset_t cpus_halted;
    550 #endif
    551 
    552 /* copy.S */
    553 int8_t	ufetch_int8(void *);
    554 int16_t	ufetch_int16(void *);
    555 int32_t ufetch_int32(void *);
    556 uint8_t	ufetch_uint8(void *);
    557 uint16_t ufetch_uint16(void *);
    558 uint32_t ufetch_uint32(void *);
    559 int8_t	ufetch_int8_intrsafe(void *);
    560 int16_t	ufetch_int16_intrsafe(void *);
    561 int32_t ufetch_int32_intrsafe(void *);
    562 uint8_t	ufetch_uint8_intrsafe(void *);
    563 uint16_t ufetch_uint16_intrsafe(void *);
    564 uint32_t ufetch_uint32_intrsafe(void *);
    565 #ifdef _LP64
    566 int64_t ufetch_int64(void *);
    567 uint64_t ufetch_uint64(void *);
    568 int64_t ufetch_int64_intrsafe(void *);
    569 uint64_t ufetch_uint64_intrsafe(void *);
    570 #endif
    571 char	ufetch_char(void *);
    572 short	ufetch_short(void *);
    573 int	ufetch_int(void *);
    574 long	ufetch_long(void *);
    575 char	ufetch_char_intrsafe(void *);
    576 short	ufetch_short_intrsafe(void *);
    577 int	ufetch_int_intrsafe(void *);
    578 long	ufetch_long_intrsafe(void *);
    579 
    580 u_char	ufetch_uchar(void *);
    581 u_short	ufetch_ushort(void *);
    582 u_int	ufetch_uint(void *);
    583 u_long	ufetch_ulong(void *);
    584 u_char	ufetch_uchar_intrsafe(void *);
    585 u_short	ufetch_ushort_intrsafe(void *);
    586 u_int	ufetch_uint_intrsafe(void *);
    587 u_long	ufetch_ulong_intrsafe(void *);
    588 void 	*ufetch_ptr(void *);
    589 
    590 int	ustore_int8(void *, int8_t);
    591 int	ustore_int16(void *, int16_t);
    592 int	ustore_int32(void *, int32_t);
    593 int	ustore_uint8(void *, uint8_t);
    594 int	ustore_uint16(void *, uint16_t);
    595 int	ustore_uint32(void *, uint32_t);
    596 int	ustore_int8_intrsafe(void *, int8_t);
    597 int	ustore_int16_intrsafe(void *, int16_t);
    598 int	ustore_int32_intrsafe(void *, int32_t);
    599 int	ustore_uint8_intrsafe(void *, uint8_t);
    600 int	ustore_uint16_intrsafe(void *, uint16_t);
    601 int	ustore_uint32_intrsafe(void *, uint32_t);
    602 #ifdef _LP64
    603 int	ustore_int64(void *, int64_t);
    604 int	ustore_uint64(void *, uint64_t);
    605 int	ustore_int64_intrsafe(void *, int64_t);
    606 int	ustore_uint64_intrsafe(void *, uint64_t);
    607 #endif
    608 int	ustore_char(void *, char);
    609 int	ustore_char_intrsafe(void *, char);
    610 int	ustore_short(void *, short);
    611 int	ustore_short_intrsafe(void *, short);
    612 int	ustore_int(void *, int);
    613 int	ustore_int_intrsafe(void *, int);
    614 int	ustore_long(void *, long);
    615 int	ustore_long_intrsafe(void *, long);
    616 int	ustore_uchar(void *, u_char);
    617 int	ustore_uchar_intrsafe(void *, u_char);
    618 int	ustore_ushort(void *, u_short);
    619 int	ustore_ushort_intrsafe(void *, u_short);
    620 int	ustore_uint(void *, u_int);
    621 int	ustore_uint_intrsafe(void *, u_int);
    622 int	ustore_ulong(void *, u_long);
    623 int	ustore_ulong_intrsafe(void *, u_long);
    624 int 	ustore_ptr(void *, void *);
    625 int	ustore_ptr_intrsafe(void *, void *);
    626 
    627 int	ustore_uint32_isync(void *, uint32_t);
    628 
    629 /* trap.c */
    630 void	netintr(void);
    631 int	kdbpeek(vaddr_t);
    632 
    633 /* mips_fpu.c */
    634 void	fpu_init(void);
    635 void	fpu_discard(void);
    636 void	fpu_load(void);
    637 void	fpu_save(void);
    638 void	fpu_save_lwp(struct lwp *);
    639 void	fpusave_cpu(struct cpu_info *);
    640 
    641 /* mips_machdep.c */
    642 void	dumpsys(void);
    643 int	savectx(struct pcb *);
    644 void	cpu_identify(device_t);
    645 
    646 /* locore*.S */
    647 int	badaddr(void *, size_t);
    648 int	badaddr64(uint64_t, size_t);
    649 
    650 /* vm_machdep.c */
    651 void	cpu_proc_fork(struct proc *, struct proc *);
    652 vaddr_t	cpu_lwp_pc(struct lwp *);
    653 void	cpu_uarea_remap(struct lwp *);
    654 
    655 #endif /* ! _LOCORE */
    656 #endif /* _KERNEL */
    657 #endif /* _CPU_H_ */
    658