cpu.h revision 1.95.4.1
1 /* $NetBSD: cpu.h,v 1.95.4.1 2011/03/05 20:51:03 rmind Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 48 #if defined(_KERNEL_OPT) 49 #include "opt_cputype.h" 50 #include "opt_lockdebug.h" 51 #include "opt_multiprocessor.h" 52 #endif 53 54 #ifndef _LOCORE 55 #include <sys/cpu_data.h> 56 #include <sys/device_if.h> 57 #include <sys/evcnt.h> 58 59 struct cpu_info { 60 struct cpu_data ci_data; /* MI per-cpu data */ 61 struct cpu_info *ci_next; /* Next CPU in list */ 62 struct cpu_softc *ci_softc; /* chip-dependent hook */ 63 device_t ci_dev; /* owning device */ 64 cpuid_t ci_cpuid; /* Machine-level identifier */ 65 u_long ci_cctr_freq; /* cycle counter frequency */ 66 u_long ci_cpu_freq; /* CPU frequency */ 67 u_long ci_cycles_per_hz; /* CPU freq / hz */ 68 u_long ci_divisor_delay; /* for delay/DELAY */ 69 u_long ci_divisor_recip; /* unused, for obsolete microtime(9) */ 70 struct lwp *ci_curlwp; /* currently running lwp */ 71 volatile int ci_want_resched; /* user preemption pending */ 72 int ci_mtx_count; /* negative count of held mutexes */ 73 int ci_mtx_oldspl; /* saved SPL value */ 74 int ci_idepth; /* hardware interrupt depth */ 75 int ci_cpl; /* current [interrupt] priority level */ 76 uint32_t ci_next_cp0_clk_intr; /* for hard clock intr scheduling */ 77 struct evcnt ci_ev_count_compare; /* hard clock intr counter */ 78 struct evcnt ci_ev_count_compare_missed; /* hard clock miss counter */ 79 struct lwp *ci_softlwps[SOFTINT_COUNT]; 80 volatile u_int ci_softints; 81 struct evcnt ci_ev_fpu_loads; /* fpu load counter */ 82 struct evcnt ci_ev_fpu_saves; /* fpu save counter */ 83 struct evcnt ci_ev_tlbmisses; 84 85 /* 86 * Per-cpu pmap information 87 */ 88 int ci_tlb_slot; /* reserved tlb entry for cpu_info */ 89 u_int ci_pmap_asid_cur; /* current ASID */ 90 struct pmap_tlb_info *ci_tlb_info; /* tlb information for this cpu */ 91 union segtab *ci_pmap_seg0tab; 92 #ifdef _LP64 93 union segtab *ci_pmap_segtab; 94 #else 95 vaddr_t ci_pmap_srcbase; /* starting VA of ephemeral src space */ 96 vaddr_t ci_pmap_dstbase; /* starting VA of ephemeral dst space */ 97 #endif 98 99 100 #ifdef MULTIPROCESSOR 101 volatile u_long ci_flags; 102 volatile uint64_t ci_request_ipis; 103 /* bitmask of IPIs requested */ 104 /* use on chips where hw cannot pass tag */ 105 uint64_t ci_active_ipis; /* bitmask of IPIs being serviced */ 106 uint32_t ci_ksp_tlb_slot; /* tlb entry for kernel stack */ 107 struct evcnt ci_evcnt_all_ipis; /* aggregated IPI counter */ 108 struct evcnt ci_evcnt_per_ipi[NIPIS]; /* individual IPI counters*/ 109 struct evcnt ci_evcnt_synci_activate_rqst; 110 struct evcnt ci_evcnt_synci_onproc_rqst; 111 struct evcnt ci_evcnt_synci_deferred_rqst; 112 struct evcnt ci_evcnt_synci_ipi_rqst; 113 114 #define CPUF_PRIMARY 0x01 /* CPU is primary CPU */ 115 #define CPUF_PRESENT 0x02 /* CPU is present */ 116 #define CPUF_RUNNING 0x04 /* CPU is running */ 117 #define CPUF_PAUSED 0x08 /* CPU is paused */ 118 #define CPUF_USERPMAP 0x20 /* CPU has a user pmap activated */ 119 #endif 120 121 }; 122 123 #define CPU_INFO_ITERATOR int 124 #define CPU_INFO_FOREACH(cii, ci) \ 125 (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next 126 127 #endif /* !_LOCORE */ 128 #endif /* _KERNEL */ 129 130 /* 131 * CTL_MACHDEP definitions. 132 */ 133 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 134 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 135 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 136 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 137 138 /* 139 * Platform can override, but note this breaks userland compatibility 140 * with other mips platforms. 141 */ 142 #ifndef CPU_MAXID 143 #define CPU_MAXID 5 /* number of valid machdep ids */ 144 #endif 145 146 #ifdef _KERNEL 147 #if defined(_MODULAR) || defined(_LKM) || defined(_STANDALONE) 148 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 149 #define MIPS1 1 150 #define MIPS3 1 151 #define MIPS4 1 152 #define MIPS32 1 153 #define MIPS64 1 154 #endif 155 156 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 157 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 158 #endif 159 160 /* Shortcut for MIPS3 or above defined */ 161 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 162 #define MIPS3_PLUS 1 163 #define __HAVE_CPU_COUNTER 164 #else 165 #undef MIPS3_PLUS 166 #endif 167 168 /* 169 * Macros to find the CPU architecture we're on at run-time, 170 * or if possible, at compile-time. 171 */ 172 173 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 174 #define CPU_ARCH_MIPS1 (1 << 0) 175 #define CPU_ARCH_MIPS2 (1 << 1) 176 #define CPU_ARCH_MIPS3 (1 << 2) 177 #define CPU_ARCH_MIPS4 (1 << 3) 178 #define CPU_ARCH_MIPS5 (1 << 4) 179 #define CPU_ARCH_MIPS32 (1 << 5) 180 #define CPU_ARCH_MIPS64 (1 << 6) 181 182 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 183 #define MIPS_CURLWP $24 184 #define MIPS_CURLWP_QUOTED "$24" 185 #define MIPS_CURLWP_LABEL _L_T8 186 #define MIPS_CURLWP_REG _R_T8 187 #define TF_MIPS_CURLWP(x) TF_REG_T8(x) 188 189 #ifndef _LOCORE 190 191 extern struct cpu_info cpu_info_store; 192 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 193 194 #define curlwp mips_curlwp 195 #define curcpu() (curlwp->l_cpu) 196 #define curpcb ((struct pcb *)lwp_getpcb(curlwp)) 197 #ifdef MULTIPROCESSOR 198 #define cpu_number() (curcpu()->ci_index) 199 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 200 #else 201 #define cpu_number() (0) 202 #define CPU_IS_PRIMARY(ci) (true) 203 #endif 204 205 /* XXX simonb 206 * Should the following be in a cpu_info type structure? 207 * And how many of these are per-cpu vs. per-system? (Ie, 208 * we can assume that all cpus have the same mmu-type, but 209 * maybe not that all cpus run at the same clock speed. 210 * Some SGI's apparently support R12k and R14k in the same 211 * box.) 212 */ 213 struct mips_options { 214 const struct pridtab *mips_cpu; 215 216 u_int mips_cpu_arch; 217 u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */ 218 u_int mips_cpu_flags; 219 u_int mips_num_tlb_entries; 220 mips_prid_t mips_cpu_id; 221 mips_prid_t mips_fpu_id; 222 bool mips_has_r4k_mmu; 223 bool mips_has_llsc; 224 u_int mips3_pg_shift; 225 u_int mips3_pg_cached; 226 #ifdef MIPS3_PLUS 227 #ifdef _LP64 228 uint64_t mips3_xkphys_cached; 229 #endif 230 uint64_t mips3_tlb_vpn_mask; 231 uint64_t mips3_tlb_pfn_mask; 232 uint32_t mips3_tlb_pg_mask; 233 #endif 234 }; 235 extern struct mips_options mips_options; 236 237 #define CPU_MIPS_R4K_MMU 0x0001 238 #define CPU_MIPS_NO_LLSC 0x0002 239 #define CPU_MIPS_CAUSE_IV 0x0004 240 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 241 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 242 #define CPU_MIPS_CACHED_CCA_SHIFT 4 243 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 244 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 245 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 246 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 247 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 248 #define CPU_MIPS_NO_LLADDR 0x1000 249 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 250 #define MIPS_NOT_SUPP 0x8000 251 252 #endif /* !_LOCORE */ 253 254 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE) 255 256 #if defined(MIPS1) 257 258 # define CPUISMIPS3 0 259 # define CPUIS64BITS 0 260 # define CPUISMIPS32 0 261 # define CPUISMIPS64 0 262 # define CPUISMIPSNN 0 263 # define MIPS_HAS_R4K_MMU 0 264 # define MIPS_HAS_CLOCK 0 265 # define MIPS_HAS_LLSC 0 266 # define MIPS_HAS_LLADDR 0 267 268 #elif defined(MIPS3) || defined(MIPS4) 269 270 # define CPUISMIPS3 1 271 # define CPUIS64BITS 1 272 # define CPUISMIPS32 0 273 # define CPUISMIPS64 0 274 # define CPUISMIPSNN 0 275 # define MIPS_HAS_R4K_MMU 1 276 # define MIPS_HAS_CLOCK 1 277 # if defined(_LOCORE) 278 # if !defined(MIPS3_4100) 279 # define MIPS_HAS_LLSC 1 280 # else 281 # define MIPS_HAS_LLSC 0 282 # endif 283 # else /* _LOCORE */ 284 # define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 285 # endif /* _LOCORE */ 286 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 287 288 #elif defined(MIPS32) 289 290 # define CPUISMIPS3 1 291 # define CPUIS64BITS 0 292 # define CPUISMIPS32 1 293 # define CPUISMIPS64 0 294 # define CPUISMIPSNN 1 295 # define MIPS_HAS_R4K_MMU 1 296 # define MIPS_HAS_CLOCK 1 297 # define MIPS_HAS_LLSC 1 298 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 299 300 #elif defined(MIPS64) 301 302 # define CPUISMIPS3 1 303 # define CPUIS64BITS 1 304 # define CPUISMIPS32 0 305 # define CPUISMIPS64 1 306 # define CPUISMIPSNN 1 307 # define MIPS_HAS_R4K_MMU 1 308 # define MIPS_HAS_CLOCK 1 309 # define MIPS_HAS_LLSC 1 310 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 311 312 #endif 313 314 #else /* run-time test */ 315 316 #ifndef _LOCORE 317 318 #define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu) 319 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 320 #define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 321 322 /* This test is ... rather bogus */ 323 #define CPUISMIPS3 ((mips_options.mips_cpu_arch & \ 324 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 325 326 /* And these aren't much better while the previous test exists as is... */ 327 #define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0) 328 #define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0) 329 #define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0) 330 #define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0) 331 #define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 332 #define CPUIS64BITS ((mips_options.mips_cpu_arch & \ 333 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 334 335 #define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) 336 337 #else /* !_LOCORE */ 338 339 #define MIPS_HAS_LLSC 0 340 341 #endif /* !_LOCORE */ 342 343 #endif /* run-time test */ 344 345 #ifndef _LOCORE 346 347 /* 348 * definitions of cpu-dependent requirements 349 * referenced in generic code 350 */ 351 352 /* 353 * Send an inter-processor interupt to each other CPU (excludes curcpu()) 354 */ 355 void cpu_broadcast_ipi(int); 356 357 /* 358 * Send an inter-processor interupt to CPUs in cpuset (excludes curcpu()) 359 */ 360 void cpu_multicast_ipi(__cpuset_t, int); 361 362 /* 363 * Send an inter-processor interupt to another CPU. 364 */ 365 int cpu_send_ipi(struct cpu_info *, int); 366 367 /* 368 * cpu_intr(ppl, pc, status); (most state needed by clockframe) 369 */ 370 void cpu_intr(int, vaddr_t, uint32_t); 371 372 /* 373 * Arguments to hardclock and gatherstats encapsulate the previous 374 * machine state in an opaque clockframe. 375 */ 376 struct clockframe { 377 vaddr_t pc; /* program counter at time of interrupt */ 378 uint32_t sr; /* status register at time of interrupt */ 379 bool intr; /* interrupted a interrupt */ 380 }; 381 382 /* 383 * A port must provde CLKF_USERMODE() for use in machine-independent code. 384 * These differ on r4000 and r3000 systems; provide them in the 385 * port-dependent file that includes this one, using the macros below. 386 */ 387 388 /* mips1 versions */ 389 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 390 391 /* mips3 versions */ 392 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 393 394 #define CLKF_PC(framep) ((framep)->pc) 395 #define CLKF_INTR(framep) ((framep)->intr) 396 397 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 398 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 399 #endif 400 401 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 402 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 403 #endif 404 405 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 406 #define CLKF_USERMODE(framep) \ 407 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 408 #endif 409 410 /* 411 * Misc prototypes and variable declarations. 412 */ 413 #define LWP_PC(l) cpu_lwp_pc(l) 414 415 struct proc; 416 struct lwp; 417 struct pcb; 418 struct reg; 419 420 /* 421 * Preempt the current process if in interrupt from user mode, 422 * or after the current trap/syscall if in system mode. 423 */ 424 void cpu_need_resched(struct cpu_info *, int); 425 /* 426 * Notify the current lwp (l) that it has a signal pending, 427 * process as soon as possible. 428 */ 429 void cpu_signotify(struct lwp *); 430 431 /* 432 * Give a profiling tick to the current process when the user profiling 433 * buffer pages are invalid. On the MIPS, request an ast to send us 434 * through trap, marking the proc as needing a profiling tick. 435 */ 436 void cpu_need_proftick(struct lwp *); 437 void cpu_set_curpri(int); 438 439 extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */ 440 441 struct cpu_info * 442 cpu_info_alloc(struct pmap_tlb_info *, cpuid_t, cpuid_t, cpuid_t, 443 cpuid_t); 444 void cpu_attach_common(device_t, struct cpu_info *); 445 void cpu_startup_common(void); 446 #ifdef _LP64 447 void cpu_vmspace_exec(struct lwp *, vaddr_t, vaddr_t); 448 #endif 449 450 #ifdef MULTIPROCESSOR 451 void cpu_hatch(struct cpu_info *ci); 452 void cpu_trampoline(void); 453 void cpu_boot_secondary_processors(void); 454 void cpu_halt(void); 455 void cpu_halt_others(void); 456 void cpu_pause(struct reg *); 457 void cpu_pause_others(void); 458 void cpu_resume(int); 459 void cpu_resume_others(void); 460 int cpu_is_paused(int); 461 void cpu_debug_dump(void); 462 463 extern volatile __cpuset_t cpus_running; 464 extern volatile __cpuset_t cpus_hatched; 465 extern volatile __cpuset_t cpus_paused; 466 extern volatile __cpuset_t cpus_resumed; 467 extern volatile __cpuset_t cpus_halted; 468 #endif 469 470 /* copy.S */ 471 int8_t ufetch_int8(void *); 472 int16_t ufetch_int16(void *); 473 int32_t ufetch_int32(void *); 474 uint8_t ufetch_uint8(void *); 475 uint16_t ufetch_uint16(void *); 476 uint32_t ufetch_uint32(void *); 477 int8_t ufetch_int8_intrsafe(void *); 478 int16_t ufetch_int16_intrsafe(void *); 479 int32_t ufetch_int32_intrsafe(void *); 480 uint8_t ufetch_uint8_intrsafe(void *); 481 uint16_t ufetch_uint16_intrsafe(void *); 482 uint32_t ufetch_uint32_intrsafe(void *); 483 #ifdef _LP64 484 int64_t ufetch_int64(void *); 485 uint64_t ufetch_uint64(void *); 486 int64_t ufetch_int64_intrsafe(void *); 487 uint64_t ufetch_uint64_intrsafe(void *); 488 #endif 489 char ufetch_char(void *); 490 short ufetch_short(void *); 491 int ufetch_int(void *); 492 long ufetch_long(void *); 493 char ufetch_char_intrsafe(void *); 494 short ufetch_short_intrsafe(void *); 495 int ufetch_int_intrsafe(void *); 496 long ufetch_long_intrsafe(void *); 497 498 u_char ufetch_uchar(void *); 499 u_short ufetch_ushort(void *); 500 u_int ufetch_uint(void *); 501 u_long ufetch_ulong(void *); 502 u_char ufetch_uchar_intrsafe(void *); 503 u_short ufetch_ushort_intrsafe(void *); 504 u_int ufetch_uint_intrsafe(void *); 505 u_long ufetch_ulong_intrsafe(void *); 506 void *ufetch_ptr(void *); 507 508 int ustore_int8(void *, int8_t); 509 int ustore_int16(void *, int16_t); 510 int ustore_int32(void *, int32_t); 511 int ustore_uint8(void *, uint8_t); 512 int ustore_uint16(void *, uint16_t); 513 int ustore_uint32(void *, uint32_t); 514 int ustore_int8_intrsafe(void *, int8_t); 515 int ustore_int16_intrsafe(void *, int16_t); 516 int ustore_int32_intrsafe(void *, int32_t); 517 int ustore_uint8_intrsafe(void *, uint8_t); 518 int ustore_uint16_intrsafe(void *, uint16_t); 519 int ustore_uint32_intrsafe(void *, uint32_t); 520 #ifdef _LP64 521 int ustore_int64(void *, int64_t); 522 int ustore_uint64(void *, uint64_t); 523 int ustore_int64_intrsafe(void *, int64_t); 524 int ustore_uint64_intrsafe(void *, uint64_t); 525 #endif 526 int ustore_char(void *, char); 527 int ustore_char_intrsafe(void *, char); 528 int ustore_short(void *, short); 529 int ustore_short_intrsafe(void *, short); 530 int ustore_int(void *, int); 531 int ustore_int_intrsafe(void *, int); 532 int ustore_long(void *, long); 533 int ustore_long_intrsafe(void *, long); 534 int ustore_uchar(void *, u_char); 535 int ustore_uchar_intrsafe(void *, u_char); 536 int ustore_ushort(void *, u_short); 537 int ustore_ushort_intrsafe(void *, u_short); 538 int ustore_uint(void *, u_int); 539 int ustore_uint_intrsafe(void *, u_int); 540 int ustore_ulong(void *, u_long); 541 int ustore_ulong_intrsafe(void *, u_long); 542 int ustore_ptr(void *, void *); 543 int ustore_ptr_intrsafe(void *, void *); 544 545 int ustore_uint32_isync(void *, uint32_t); 546 547 /* trap.c */ 548 void netintr(void); 549 int kdbpeek(vaddr_t); 550 551 /* mips_fpu.c */ 552 void fpu_init(void); 553 void fpu_discard(void); 554 void fpu_load(void); 555 void fpu_save(void); 556 void fpu_save_lwp(struct lwp *); 557 bool fpu_used_p(struct lwp *); 558 559 /* mips_machdep.c */ 560 void dumpsys(void); 561 int savectx(struct pcb *); 562 void cpu_identify(device_t); 563 564 /* locore*.S */ 565 int badaddr(void *, size_t); 566 int badaddr64(uint64_t, size_t); 567 568 /* vm_machdep.c */ 569 void * cpu_uarea_alloc(bool); 570 bool cpu_uarea_free(void *); 571 void cpu_proc_fork(struct proc *, struct proc *); 572 vaddr_t cpu_lwp_pc(struct lwp *); 573 int ioaccess(vaddr_t, paddr_t, vsize_t); 574 int iounaccess(vaddr_t, vsize_t); 575 576 #endif /* ! _LOCORE */ 577 #endif /* _KERNEL */ 578 #endif /* _CPU_H_ */ 579
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