1 /* ********************************************************************* 2 * BCM1280/BCM1400 Board Support Package 3 * 4 * SCD Constants and Macros File: bcm1480_scd.h 5 * 6 * This module contains constants and macros useful for 7 * manipulating the System Control and Debug module. 8 * 9 * BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03) 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003,2004,2005 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48 #ifndef _BCM1480_SCD_H 49 #define _BCM1480_SCD_H 50 51 #include "sb1250_defs.h" 52 53 /* ********************************************************************* 54 * Pull in the BCM1250's SCD since lots of stuff is the same. 55 ********************************************************************* */ 56 57 #include "sb1250_scd.h" 58 59 /* ********************************************************************* 60 * Some general notes: 61 * 62 * This file is basically a "what's new" header file. Since the 63 * BCM1250 and the new BCM1480 (and derivatives) share many common 64 * features, this file contains only what's new or changed from 65 * the 1250. (above, you can see that we include the 1250 symbols 66 * to get the base functionality). 67 * 68 * In software, be sure to use the correct symbols, particularly 69 * for blocks that are different between the two chip families. 70 * All BCM1480-specific symbols have _BCM1480_ in their names, 71 * and all BCM1250-specific and "base" functions that are common in 72 * both chips have no special names (this is for compatibility with 73 * older include files). Therefore, if you're working with the 74 * SCD, which is very different on each chip, A_SCD_xxx implies 75 * the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480 76 * version. 77 ********************************************************************* */ 78 79 /* ********************************************************************* 80 * System control/debug registers 81 ********************************************************************* */ 82 83 /* 84 * System Identification and Revision Register (Table 12) 85 * Register: SCD_SYSTEM_REVISION 86 * This register is field compatible with the 1250. 87 */ 88 89 /* 90 * New part definitions 91 */ 92 93 #define K_SYS_PART_BCM1480 0x1406 94 #define K_SYS_PART_BCM1280 0x1206 95 #define K_SYS_PART_BCM1455 0x1407 96 #define K_SYS_PART_BCM1255 0x1257 97 #define K_SYS_PART_BCM1158 0x1156 98 99 /* 100 * Manufacturing Information Register (Table 14) 101 * Register: SCD_SYSTEM_MANUF 102 */ 103 104 /* 105 * System Configuration Register (Table 15) 106 * Register: SCD_SYSTEM_CFG 107 * Entire register is different from 1250, all new constants below 108 */ 109 110 #define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0) 111 #define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1) 112 #define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2) 113 #define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3) 114 #define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4) 115 #define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) 116 117 #define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) 118 #define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_PLL_DIV) 119 #define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_PLL_DIV) 120 #define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_PLL_DIV,M_BCM1480_SYS_PLL_DIV) 121 122 #define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) 123 #define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5,S_BCM1480_SYS_SW_DIV) 124 #define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_SW_DIV) 125 #define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x,S_BCM1480_SYS_SW_DIV,M_BCM1480_SYS_SW_DIV) 126 127 #define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) 128 #define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) 129 130 #define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) 131 #define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2,S_BCM1480_SYS_BOOT_MODE) 132 #define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_BOOT_MODE) 133 #define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_BCM1480_SYS_BOOT_MODE,M_BCM1480_SYS_BOOT_MODE) 134 #define K_BCM1480_SYS_BOOT_MODE_ROM32 0 135 #define K_BCM1480_SYS_BOOT_MODE_ROM8 1 136 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2 137 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG 3 138 #define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19) 139 140 #define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20) 141 #define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21) 142 #define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) 143 #define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23) 144 #define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24) 145 #define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) 146 147 #define S_BCM1480_SYS_CONFIG 26 148 #define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6,S_BCM1480_SYS_CONFIG) 149 #define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_CONFIG) 150 #define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x,S_BCM1480_SYS_CONFIG,M_BCM1480_SYS_CONFIG) 151 152 #define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32,15) 153 154 #define S_BCM1480_SYS_NODEID 47 155 #define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4,S_BCM1480_SYS_NODEID) 156 #define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x,S_BCM1480_SYS_NODEID) 157 #define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x,S_BCM1480_SYS_NODEID,M_BCM1480_SYS_NODEID) 158 159 #define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) 160 #define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) 161 #define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53) 162 #define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54) 163 #define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55) 164 #define S_BCM1480_SYS_DISABLECPU0 56 165 #define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0) 166 #define S_BCM1480_SYS_DISABLECPU1 57 167 #define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1) 168 #define S_BCM1480_SYS_DISABLECPU2 58 169 #define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2) 170 #define S_BCM1480_SYS_DISABLECPU3 59 171 #define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3) 172 173 #define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60) 174 #define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61) 175 #define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62) 176 #define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63) 177 178 /* 179 * Scratch Register (Table 16) 180 * Register: SCD_SYSTEM_SCRATCH 181 * Same as BCM1250 182 */ 183 184 185 /* 186 * Mailbox Registers (Table 17) 187 * Registers: SCD_MBOX_{0,1}_CPU_x 188 * Same as BCM1250 189 */ 190 191 192 /* 193 * See bcm1480_int.h for interrupt mapper registers. 194 */ 195 196 197 /* 198 * Watchdog Timer Initial Count Registers (Table 23) 199 * Registers: SCD_WDOG_INIT_CNT_x 200 * 201 * The watchdogs are almost the same as the 1250, except 202 * the configuration register has more bits to control the 203 * other CPUs. 204 */ 205 206 207 /* 208 * Watchdog Timer Configuration Registers (Table 25) 209 * Registers: SCD_WDOG_CFG_x 210 */ 211 212 #define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) 213 214 #define S_BCM1480_SCD_WDOG_RESET_TYPE 2 215 #define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5,S_BCM1480_SCD_WDOG_RESET_TYPE) 216 #define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE) 217 #define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_BCM1480_SCD_WDOG_RESET_TYPE,M_BCM1480_SCD_WDOG_RESET_TYPE) 218 219 #define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ 220 #define K_BCM1480_SCD_WDOG_RESET_SOFT 1 221 #define K_BCM1480_SCD_WDOG_RESET_CPU0 3 222 #define K_BCM1480_SCD_WDOG_RESET_CPU1 5 223 #define K_BCM1480_SCD_WDOG_RESET_CPU2 9 224 #define K_BCM1480_SCD_WDOG_RESET_CPU3 17 225 #define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS 31 226 227 228 #define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8) 229 230 /* 231 * General Timer Initial Count Registers (Table 26) 232 * Registers: SCD_TIMER_INIT_x 233 * 234 * The timer registers are the same as the BCM1250 235 */ 236 237 238 /* 239 * ZBbus Count Register (Table 29) 240 * Register: ZBBUS_CYCLE_COUNT 241 * 242 * Same as BCM1250 243 */ 244 245 /* 246 * ZBbus Compare Registers (Table 30) 247 * Registers: ZBBUS_CYCLE_CPx 248 * 249 * Same as BCM1250 250 */ 251 252 253 /* 254 * System Performance Counter Configuration Register (Table 31) 255 * Register: PERF_CNT_CFG_0 256 * 257 * SPC_CFG_SRC[0-3] is the same as the 1250. 258 * SPC_CFG_SRC[4-7] only exist on the 1480 259 * The clear/enable bits are in different locations on the 1250 and 1480. 260 */ 261 262 #define S_SPC_CFG_SRC4 32 263 #define M_SPC_CFG_SRC4 _SB_MAKEMASK(8,S_SPC_CFG_SRC4) 264 #define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC4) 265 #define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x,S_SPC_CFG_SRC4,M_SPC_CFG_SRC4) 266 267 #define S_SPC_CFG_SRC5 40 268 #define M_SPC_CFG_SRC5 _SB_MAKEMASK(8,S_SPC_CFG_SRC5) 269 #define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC5) 270 #define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x,S_SPC_CFG_SRC5,M_SPC_CFG_SRC5) 271 272 #define S_SPC_CFG_SRC6 48 273 #define M_SPC_CFG_SRC6 _SB_MAKEMASK(8,S_SPC_CFG_SRC6) 274 #define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC6) 275 #define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x,S_SPC_CFG_SRC6,M_SPC_CFG_SRC6) 276 277 #define S_SPC_CFG_SRC7 56 278 #define M_SPC_CFG_SRC7 _SB_MAKEMASK(8,S_SPC_CFG_SRC7) 279 #define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC7) 280 #define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x,S_SPC_CFG_SRC7,M_SPC_CFG_SRC7) 281 282 /* 283 * System Performance Counter Control Register (Table 32) 284 * Register: PERF_CNT_CFG_1 285 * BCM1480 specific 286 */ 287 #define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) 288 #define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1) 289 #if SIBYTE_HDR_FEATURE_CHIP(1480) 290 #define M_SPC_CFG_CLEAR M_BCM1480_SPC_CFG_CLEAR 291 #define M_SPC_CFG_ENABLE M_BCM1480_SPC_CFG_ENABLE 292 #endif 293 294 /* 295 * System Performance Counters (Table 33) 296 * Registers: PERF_CNT_x 297 */ 298 299 #define S_BCM1480_SPC_CNT_COUNT 0 300 #define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40,S_BCM1480_SPC_CNT_COUNT) 301 #define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CNT_COUNT) 302 #define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x,S_BCM1480_SPC_CNT_COUNT,M_BCM1480_SPC_CNT_COUNT) 303 304 #define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) 305 306 307 /* 308 * Bus Watcher Error Status Register (Tables 36, 37) 309 * Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG 310 * Same as BCM1250. 311 */ 312 313 /* 314 * Bus Watcher Error Data Registers (Table 38) 315 * Registers: BUS_ERR_DATA_x 316 * Same as BCM1250. 317 */ 318 319 /* 320 * Bus Watcher L2 ECC Counter Register (Table 39) 321 * Register: BUS_L2_ERRORS 322 * Same as BCM1250. 323 */ 324 325 326 /* 327 * Bus Watcher Memory and I/O Error Counter Register (Table 40) 328 * Register: BUS_MEM_IO_ERRORS 329 * Same as BCM1250. 330 */ 331 332 333 /* 334 * Address Trap Registers 335 * 336 * Register layout same as BCM1250, almost. The bus agents 337 * are different, and the address trap configuration bits are 338 * slightly different. 339 */ 340 341 #define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4,0) 342 #define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40,0) 343 344 #define S_BCM1480_ATRAP_CFG_CNT 0 345 #define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_BCM1480_ATRAP_CFG_CNT) 346 #define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CNT) 347 #define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CNT,M_BCM1480_ATRAP_CFG_CNT) 348 349 #define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) 350 #define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) 351 #define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5) 352 #define M_BCM1480_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) 353 #define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) 354 355 #define S_BCM1480_ATRAP_CFG_AGENTID 8 356 #define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_BCM1480_ATRAP_CFG_AGENTID) 357 #define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID) 358 #define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_AGENTID,M_BCM1480_ATRAP_CFG_AGENTID) 359 360 361 #define K_BCM1480_BUS_AGENT_CPU0 0 362 #define K_BCM1480_BUS_AGENT_CPU1 1 363 #define K_BCM1480_BUS_AGENT_NC 2 364 #define K_BCM1480_BUS_AGENT_IOB 3 365 #define K_BCM1480_BUS_AGENT_SCD 4 366 #define K_BCM1480_BUS_AGENT_L2C 6 367 #define K_BCM1480_BUS_AGENT_MC 7 368 #define K_BCM1480_BUS_AGENT_CPU2 8 369 #define K_BCM1480_BUS_AGENT_CPU3 9 370 #define K_BCM1480_BUS_AGENT_PM 10 371 372 #define S_BCM1480_ATRAP_CFG_CATTR 12 373 #define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2,S_BCM1480_ATRAP_CFG_CATTR) 374 #define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_BCM1480_ATRAP_CFG_CATTR) 375 #define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_BCM1480_ATRAP_CFG_CATTR,M_BCM1480_ATRAP_CFG_CATTR) 376 377 #define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0 378 #define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 379 #define K_BCM1480_ATRAP_CFG_CATTR_NONCOH 2 380 #define K_BCM1480_ATRAP_CFG_CATTR_COHERENT 3 381 382 #define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14) 383 384 385 /* 386 * Trace Event Registers (Table 47) 387 * Same as BCM1250. 388 */ 389 390 /* 391 * Trace Sequence Control Registers (Table 48) 392 * Registers: TRACE_SEQUENCE_x 393 * 394 * Same as BCM1250 except for two new fields. 395 */ 396 397 398 #define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25) 399 400 #define S_BCM1480_SCD_TRSEQ_SWFUNC 26 401 #define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2,S_BCM1480_SCD_TRSEQ_SWFUNC) 402 #define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC) 403 #define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRSEQ_SWFUNC,M_BCM1480_SCD_TRSEQ_SWFUNC) 404 405 /* 406 * Trace Control Register (Table 49) 407 * Register: TRACE_CFG 408 * 409 * BCM1480 changes to this register (other than location of the CUR_ADDR field) 410 * are defined below. 411 */ 412 413 #define S_BCM1480_SCD_TRACE_CFG_MODE 16 414 #define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE) 415 #define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE) 416 #define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE,M_BCM1480_SCD_TRACE_CFG_MODE) 417 418 #define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0 419 #define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 420 #define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2 421 422 #endif /* _BCM1480_SCD_H */ 423
Indexes created Mon Sep 29 18:09:42 GMT 2025