Revert rename back to OFSET, since the name follows historical PGOFSET definition. Noted by tsutsui.

Fix all remaining typos, mainly in comments but also in few definitions and log messages, reported by me in PR kern/54889.
Also fixed some additional typos in comments, found on review of same files or typos.

branches: 1.51.12;
sh3: make ASTs work as expected, and fix a few things in the TLB refill path.
With help from uwe@ and martin@.

branches: 1.50.16;
* Split sys/kern/sys_process.c into three parts:
1 - ptrace(2) syscall for native emulation
2 - common ptrace(2) syscall code (shared with compat_netbsd32)
3 - support routines that are shared with PROCFS and/or KTRACE

* Add module glue for #1 and #2. Both modules will be built-in to the
kernel if "options PTRACE" is included in the config file (this is
the default, defined in sys/conf/std).

* Mark the ptrace(2) syscall as modular in syscalls.master (generated
files will be committed shortly).

* Conditionalize all remaining portions of PTRACE code on a new kernel
option PTRACE_HOOKS.

XXX Instead of PROCFS depending on 'options PTRACE', we should probably
just add a procfs attribute to the sys/kern/sys_process.c file's
entry in files.kern, and add PROCFS to the "#if defineds" for
process_domem(). It's really confusing to have two different ways
of requiring this file.

branches: 1.49.14; 1.49.32; 1.49.36;
Use __INTR_MASK_EXCEPTION_UNBLOCK combo.

__EXCEPTION_ENTRY - "tst" already does logical AND, so shave off extra
"mov" and "and" and just test PSL_MD bit directly.

While here - shuffle around instructions to construct PSL_MD to break
dependencies.

While still here - only interrupt vector uses SSR and SPC as function
args, so don't bother saving them here in r4 and r5. Other vectors
don't need them and interrupt vector can just as well "stc" them
directly before exceptions are enabled.

Implement PT_STEP.

branches: 1.46.2; 1.46.4;
Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits. Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

branches: 1.45.6;
Revert two previous revisions and just use __pmap_kernel directly again.
There's no reason to pretend we don't know what kernel_pmap_ptr is.

__pmap_kernel is pointer not symbol from pmap.c 1.68. set correct address.

Make pmap_kernel() a MI macro for struct pmap *kernel_pmap_ptr,
which is now the "API" provided by the pmap module. pmap_kernel()
remains as the syntactic sugar.

Bonus cosmetics round: move all the pmap_t pointer typedefs into
uvm_pmap.h.

Thanks to Greg Oster for providing cpu muscle for doing test builds.

branches: 1.42.4; 1.42.6;
sh_vector_generic - reorder literals to improve locality of reference.

Match PC address for single-stepping, program BARA = tf->tf_spc before
returning from exception.

Makes single-stepping work on sh3 - without matching the address sh3
gets stuck at the instruction we are at, getting EXPEVT_BREAK before
executing the instruction.

Bah, got tf_ubc = 0 logic wrong in previous. Revert that part, it's bogus.

Support single-stepping in DDB for sh3 too, it has different format of
UBC registers.

branches: 1.38.2;
Remove clause 3 and 4 from TNF licenses

branches: 1.37.2; 1.37.4;
Revert interrupt stack changes. There are some issues and, at least
in the current form, they complicate implementation of fast software
interrupts. I'd rather get fast softints in now and may be revisit
interrupt stack later.

Now that __EXCEPTION_BLOCK does the right thing, preserving SR for us,
we don't have to open-code it here.

branches: 1.35.2; 1.35.6;
If we are returning from a nested interrupt we know we are returning
to kernel so we can skip the PSL_MD check.

Use dedicated interrupt stack. Tested on hpcsh and landisk. This has
been sitting in my tree for quite a while. While here s/top/bottom/
in a few places related to stacks to confirm to conventional
terminology.

branches: 1.33.2; 1.33.4; 1.33.8;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

sh_vector_interrupt - while here, shave off a few cycles and run with
exceptions disabled only the code that really needs to.

Do RAS check in sh_vector_interrupt, don't abuse ast() for that.

branches: 1.30.2; 1.30.4;
Add back comma between operands lost in s/tab/space/ cosmetics of 1.21
(as(1) doesn't mind, apparently)

branches: 1.29.4; 1.29.8;
Implement fast path TLB miss handling. Walk the page table without
creating a trapframe, with exceptions disabled and using only BANK1
registers. If a valid pte is found, load it and return. Otherwise
create a trapframe and proceed to the full-blown C handler.

branches: 1.28.4;
Don't do curupte checks if the miss address is in user space.

Shave off few instructions when doing ldtlb.

Cosmetic - fix local label name to match the name of the var it refers.

Use dt to loop over md_upte in sh3_vector_tlbmiss. Saves a few instructions.

Comment sh3_vector_tlbmiss. Same object code is generated.

Arrange for data blocks to start on 32B cache line boundary.

Use .L* for local labels. Misc cosmetic.
Same object code is generated.

branches: 1.21.2;
s/TAB/space/ to separate instruction operands. There are quite a few
cpp macros and long src operands anyway that destroy any intended
"neatly lined up" effect that TAB was supposed to achieve.

White space change only, same object code is generated, but it is much
easier on the eyes now.

branches: 1.20.2; 1.20.4; 1.20.8; 1.20.10; 1.20.12;
Don't truncate TEA when we call tlb_exception from sh_vector_generic.

branches: 1.19.2; 1.19.4;
Follow up to revision 1.16 (that only dealt with sh3).
Pass untruncated va=TEA to tlb_exception() from sh4_vector_tlbmiss too.

branches: 1.18.2;
sh3_vector_tlbmiss: don't waste perfectly good delay slots.

While here, shave off few bytes and few cycles off of the sh3_vector_tlbmiss.

Since the registers we use are at the very end of address space, we
can load their addresses as small immediate negative constants instead
of loading them from memory.

Pass untruncated va=TEA to tlb_exception(), not its VPN.

branches: 1.15.2; 1.15.4;
Use macros from <machine/asm.h>. Provide .size
Provide LINTSTUBs.

branches: 1.14.2;
merge ktrace-lwp.

branches: 1.13.16;
Cosmetic: in sh_vector_generic use named label instead of numeric
label for the curlwp address. Same object code is generated.

Add __KERNEL_RCSID.

Pass TEA to general_exception. While here add a couple of comments.

branches: 1.10.2;
Merge the nathanw_sa branch.

branches: 1.9.6;
rework general exception, and TLB exception handling for new pmap.
all exception staffs are moved to exception.[ch]

Use "#define<tab>", white space nits.

make these compile with gcc -O0

add uvmexp.intrs++

Rework interrupt code.
+ Fully utilize SH SR.I[0:3] interrupt level.
+ software interrupt is emulated by TMU1, 2 one shot interrupt.
+ implement generic soft interrupts.
+ implement clockframe correctly.

cosmetic changes, fix comments.

kernel stack fix. old code simply P3 address converted to P1, it
caused memory destruction when kernel stack grow over 1 page. new
code use P3 address for kernel stack. but for the sake of debug, P1
kernel stack mode remain.

branches: 1.2.2; 1.2.8;
Change foo_r0_r1 macro in sh3/locore.h to foo(Rn, Rm)

Move common exception vector and scheduler code to
sh3/sh3/exception_vector.S and sh3/sh3/locore_subr.S. exception
vectors are installed by sh_cpu_init(). machine/locore.S contains
kernel entry, interrupt handler, and some MD code.