| /src/external/gpl3/gcc/dist/libgcc/config/rs6000/ |
| crtdbase.S | 28 .csect __gcc_unwind_dbase[RW],2
|
| /src/external/gpl3/gcc.old/dist/libgcc/config/rs6000/ |
| crtdbase.S | 28 .csect __gcc_unwind_dbase[RW],2
|
| /src/sys/dev/microcode/aic7xxx/ |
| aic79xx.reg | 99 access_mode RW
113 access_mode RW
130 access_mode RW
256 access_mode RW
272 access_mode RW
281 access_mode RW
289 access_mode RW
325 access_mode RW
334 access_mode RW
344 access_mode RW
[all...] |
| aic7xxx.reg | 59 access_mode RW
76 access_mode RW
92 access_mode RW
169 access_mode RW
185 access_mode RW
207 access_mode RW
212 access_mode RW
225 access_mode RW
231 access_mode RW
240 access_mode RW
[all...] |
| aicasm_symbol.h | 71 RW = 0x03
|
| aicasm_scan.l | 171 RW|RO|WO {
172 if (strcmp(yytext, "RW") == 0)
173 yylval.value = RW;
|
| /src/sys/dev/ic/ |
| arn9380.c | 317 reg = RW(reg, AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL,
323 reg = RW(reg, AR_PHY_65NM_CH0_TOP_XPABIASLVL,
327 reg = RW(reg, AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB,
335 reg = RW(reg, AR_SWITCH_TABLE_COM_ALL, modal->antCtrlCommon);
338 reg = RW(reg, AR_SWITCH_TABLE_COM_2_ALL, modal->antCtrlCommon2);
344 reg = RW(reg, AR_SWITCH_TABLE_ALL, modal->antCtrlChain[i]);
351 reg = RW(reg, AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL,
369 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_0, 5);
370 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_1, 5);
371 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_2, 5)
[all...] |
| arn9285.c | 195 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, modal->iqCalI);
196 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, modal->iqCalQ);
201 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
203 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
205 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
207 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
213 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
215 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
217 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
219 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB
[all...] |
| arn9287.c | 176 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
178 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
183 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
185 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
190 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,
192 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,
200 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
203 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
207 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
217 reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn)
[all...] |
| arn9280.c | 221 reg = RW(reg, AR_AN_SYNTH9_REFDIVA, 1);
257 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
259 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
265 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
267 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
269 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
271 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
280 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,
282 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,
288 reg = RW(reg, AR_AN_RF2G1_CH0_OB, modal->ob)
[all...] |
| arn5416.c | 248 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
250 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
259 reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_MARGIN,
261 reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_ATTEN,
270 reg = RW(reg, AR_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);
274 reg = RW(reg, AR_PHY_GAIN_2GHZ_RXTX_MARGIN,
279 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
283 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
284 reg = RW(reg, AR_PHY_DESIRED_SZ_PGA, modal->pgaDesiredSize);
294 reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn)
[all...] |
| arn9003.c | 588 reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);
844 reg = RW(reg, AR_RXBP_THRESH_HP, 1);
845 reg = RW(reg, AR_RXBP_THRESH_LP, 1);
1953 reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp);
1954 reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man);
1963 reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp);
1964 reg = RW(reg, AR_PHY_SGI_DSC_MAN, man);
2059 reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]);
2063 reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);
2218 reg = RW(reg, AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, 10)
[all...] |
| arn5008.c | 458 reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);
1778 reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp);
1779 reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man);
1788 reg = RW(reg, AR_PHY_HALFGI_DSC_EXP, exp);
1789 reg = RW(reg, AR_PHY_HALFGI_DSC_MAN, man);
1892 reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]);
1896 reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);
1991 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, log);
2079 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, i_coff);
2080 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, q_coff)
[all...] |
| /src/usr.bin/uuencode/ |
| uuencode.c | 99 #define RW (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH)
100 mode = RW & ~umask(RW);
|
| /src/sys/external/bsd/compiler_rt/dist/lib/tsan/tests/rtl/ |
| tsan_test_util_posix.cc | 110 else if (type_ == RW)
133 else if (type_ == RW)
145 else if (type_ == RW)
157 else if (type_ == RW)
170 else if (type_ == RW)
176 CHECK(type_ == RW);
182 CHECK(type_ == RW);
188 CHECK(type_ == RW);
|
| tsan_test_util.h | 36 RW,
|
| tsan_mop.cc | 69 Mutex m(Mutex::RW);
88 Mutex m(Mutex::RW);
|
| tsan_mutex.cc | 60 Mutex m(Mutex::RW);
128 Mutex m(Mutex::RW);
|
| /src/usr.sbin/lpr/common_source/ |
| lp.h | 68 extern long RW; /* open LP for reading and writing */
|
| /src/external/bsd/ntp/dist/ntpd/ |
| cmd_args.c | 162 set_sys_var(v_assign, strlen(v_assign) + 1, RW);
174 (u_short) (RW | DEF));
|
| /src/external/apache2/llvm/dist/llvm/lib/MC/MCDisassembler/ |
| MCDisassembler.cpp | 62 SMC_PCASE(RW, 1)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonBitTracker.cpp | 94 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
101 return IsSubLo ? BT::BitMask(0, RW-1)
102 : BT::BitMask(RW, 2*RW-1);
274 // Extract RW low bits of the cell.
275 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
277 assert(RW <= RC.width());
278 return eXTR(RC, 0, RW);
280 // Extract RW high bits of the cell.
281 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
[all...] |
| /src/external/apache2/llvm/dist/clang/utils/ABITest/ |
| Enumeration.py | 152 LW,RW = W//2, W - (W//2)
153 L,R = getNthPairBounded(N, H**LW, H**RW)
155 getNthNTuple(R,RW,H=H,useLeftToRight=useLeftToRight))
|
| /src/external/gpl3/gdb.old/dist/sim/cr16/ |
| cr16-sim.h | 384 #define RW(addr) sim_core_read_unaligned_2 (cpu, PC, read_map, addr)
391 return (RW (addr) << 16) | RW (addr + 2);
|
| /src/external/gpl3/gdb/dist/sim/cr16/ |
| cr16-sim.h | 384 #define RW(addr) sim_core_read_unaligned_2 (cpu, PC, read_map, addr)
391 return (RW (addr) << 16) | RW (addr + 2);
|
