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    Searched refs:c0 (Results 1 - 25 of 131) sorted by relevancy

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  /src/sys/arch/arm/arm/
cpufunc_asm_arm67.S 53 mcrne p15, 0, r2, c7, c0, 0
56 mcr p15, 0, r0, c2, c0, 0
59 mcrne p15, 0, r0, c5, c0, 0
62 mcrne p15, 0, r0, c7, c0, 0
74 mcr p15, 0, r0, c5, c0, 0
78 mcr p15, 0, r0, c6, c0, 0
85 mcr p15, 0, r0, c7, c0, 0
96 mcr p15, 0, r0, c7, c0, 0 /* flush cache */
99 mcr p15, 0, r0, c2, c0, 0
102 mcr p15, 0, r0, c5, c0,
    [all...]
cpufunc_asm.S 58 * c0 - CPU ID
65 mrc p15, 0, r0, c0, c0, 0
70 mrc p15, 0, r0, c0, c0, 1
75 mrc p15, 0, r0, c1, c0, 0
80 mrc p15, 0, r0, c5, c0, 0
85 mrc p15, 0, r0, c6, c0, 0
103 mcr p15, 0, r0, c1, c0, 0
108 mcr p15, 0, r0, c3, c0,
    [all...]
cpufunc_asm_arm1136.S 42 mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
armv6_start.S 108 mrc p15, 0, R_TMP1, c1, c0, 0
110 mcr p15, 0, R_TMP1, c1, c0, 0
157 mrc p15, 0, r0, c0, c0, 0 // MIDR
160 mrc p15, 0, r0, c0, c0, 6 // REVIDR
163 mrc p15, 0, r0, c0, c0, 5 // MPIDR
166 mrc p15, 0, r0, c2, c0, 0 // TTBR0 read
170 mrc p15, 0, r0, c2, c0, 1 // TTBR1 rea
    [all...]
cpufunc_asm_ixp12x0.S 54 mcr p15, 0, r0, c2, c0, 0
66 mcr p15, 0, r0, c9, c0, 0 /* drain read buffer */
  /src/lib/libc/locale/
_wctrans.c 82 __nbrune_t c0; local in function:_towctrans_ext
92 c0 = (__nbrune_t)c; /* XXX assumes wchar_t = int */
97 if (re->re_min <= c0 && re->re_max >= c0)
98 return (re->re_map + c0 - re->re_min);
99 else if (c0 >= re->re_max) {
  /src/sys/arch/evbarm/iq80310/
iq80310_start.S 53 mrc p15, 0, r2, c1, c0, 0
55 mcr p15, 0, r2, c1, c0, 0
113 mcr p15, 0, r0, c2, c0, 0
120 mcr p15, 0, r0, c3, c0, 0
126 mrc p15, 0, r2, c1, c0, 0
128 mcr p15, 0, r2, c1, c0, 0
135 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */
  /src/sys/arch/evbarm/ixm1200/
ixm1200_start.S 62 mrc p15, 0, r0, c1, c0 ,0 /* read ctrl */
72 mcr p15, 0, r0, c1, c0 ,0 /* write ctrl */
80 mcr p15, 0, r0, c2, c0 ,0 /* write trans table base */
84 mcr p15, 0, r0, c3, c0 ,0 /* write domain */
94 mcr p15, 0, r0, c9, c0 ,0 /* flush all entries */
95 mcr p15, 0, r0, c9, c0 ,4 /* disable user mode MCR access */
99 mcr p15, 0, r0, c13, c0 ,0 /* process ID 0
103 mcr p15, 0, r0, c15, c0 ,0 /* DBAR = 0 */
153 mcr p15, 0, r0, c2, c0 ,0 /* write trans table base */
160 mrc p15, 0, r1, c1, c0 ,0 /* read ctrl *
    [all...]
  /src/lib/libc/arch/arm/sys/
__aeabi_read_tp.S 12 mrc p15, 0, r0, c13, c0, 3
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/volt/
gk20a.h 29 int c0; member in struct:cvb_coef
  /src/sys/arch/evbarm/g42xxeb/
g42xxeb_start.S 52 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
98 mrc p15, 0, r0, c2, c0, 0 /* get ttb prepared by redboot */
102 mrc p15, 0, r2, c1, c0, 0
123 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
128 mcr p15, 0, r0, c3, c0, 0
131 mrc p15, 0, r0, c1, c0, 0
133 mcr p15, 0, r0, c1, c0, 0
  /src/sys/arch/evbarm/iq80321/
iq80321_start.S 59 mrc p15, 0, r2, c1, c0, 0
61 mcr p15, 0, r2, c1, c0, 0
122 mcr p15, 0, r0, c2, c0, 0
129 mcr p15, 0, r0, c3, c0, 0
135 mrc p15, 0, r2, c1, c0, 0
137 mcr p15, 0, r2, c1, c0, 0
144 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */
  /src/sys/arch/evbarm/lubbock/
lubbock_start.S 52 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
98 mrc p15, 0, r0, c2, c0, 0 /* get ttb prepared by redboot */
102 mrc p15, 0, r2, c1, c0, 0
123 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
128 mcr p15, 0, r0, c3, c0, 0
131 mrc p15, 0, r0, c1, c0, 0
133 mcr p15, 0, r0, c1, c0, 0
  /src/sys/arch/zaurus/zaurus/
zaurus_start.S 48 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
80 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
85 mcr p15, 0, r0, c3, c0, 0
88 mrc p15, 0, r0, c1, c0, 0
91 mcr p15, 0, r0, c1, c0, 0
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/sec/fuc/
g98.fuc0s 514 cxsin $c0
515 cxsout $c0
525 cxsin $c0
526 cenc $c0 $c0
527 cxsout $c0
533 cxsin $c0
534 cdec $c0 $c0
535 cxsout $c0
    [all...]
  /src/sys/arch/evbarm/armadaxp/
armadaxp_start.S 72 mrc p15, 0, r2, c1, c0, 0
77 mcr p15, 0, r2, c1, c0, 0
101 mcr p15, 0, r0, c2, c0, 0 // Set TTBR0
103 mcr p15, 0, r0, c2, c0, 1 // Set TTBR1
108 mcr p15, 0, r0, c2, c0, 2 // TTBCR write
113 mcr p15, 0, r0, c13, c0, 1 // CONTEXTIDR write: Set ASID to 0
117 mcr p15, 0, r0, c3, c0, 0 // DACR write
123 mrc p15, 0, r0, c1, c0, 0
129 mcr p15, 0, r0, c1, c0, 0
  /src/sys/arch/evbarm/gumstix/
gumstix_start.S 87 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ; \
105 mrc p15, 0, ip, c1, c0, 0
107 mcr p15, 0, ip, c1, c0, 0
128 mrc p15, 0, r1, c0, c0, 0
171 mcr p15, 0, r1, c2, c0, 0 /* Set TTB */
180 mcr p15, 0, r1, c3, c0, 0
183 mrc p15, 0, r1, c1, c0, 0
188 mcr p15, 0, r1, c1, c0, 0
  /src/sys/arch/shark/stand/ofwboot/
srt0.S 44 mrc p15, 0, r0, c0, c0, 0
  /src/sys/arch/evbarm/imx31/
imx31lk_start.S 57 mrc p15, 0, r0, c2, c0, 0 /* L1 table addr into r0 */
59 mcr p15, 0, r0, c2, c0, 1 /* copy it to TTBR1 */
61 mcr p15, 0, r3, c2, c0, 2 /* set TTBCR to enable TTBR1 */
91 mcr p15, 0, r0, c3, c0, 0
  /src/sys/arch/netwinder/netwinder/
nwmmu.S 102 mcr p15, 0, r0, c2, c0, 0
109 mcr p15, 0, r0, c3, c0, 0
112 mrc p15, 0, r2, c1, c0, 0
114 mcr p15, 0, r2, c1, c0, 0
  /src/sys/stand/efiboot/bootarm/
cache.S 37 mcr p15, 2, ip, c0, c0, 0 @ set cache level to L1
38 mrc p15, 1, r2, c0, c0, 0 @ read CCSIDR
58 mrc p15, 1, r0, c0, c0, 1 @ read CLIDR
69 mcr p15, 2, r3, c0, c0, 0 @ select cache level
71 mrc p15, 1, r0, c0, c0, 0 @ read CCSID
    [all...]
  /src/sys/arch/evbarm/adi_brh/
brh_start.S 69 mrc p15, 0, r2, c1, c0, 0
71 mcr p15, 0, r2, c1, c0, 0
160 mcr p15, 0, r0, c2, c0, 0
167 mcr p15, 0, r0, c3, c0, 0
173 mrc p15, 0, r2, c1, c0, 0
175 mcr p15, 0, r2, c1, c0, 0
182 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */
  /src/sys/arch/evbarm/hdl_g/
hdlg_start.S 59 mrc p15, 0, r2, c1, c0, 0
61 mcr p15, 0, r2, c1, c0, 0
165 mcr p15, 0, r0, c2, c0, 0
172 mcr p15, 0, r0, c3, c0, 0
178 mrc p15, 0, r2, c1, c0, 0
180 mcr p15, 0, r2, c1, c0, 0
187 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */
  /src/sys/arch/evbarm/ixdp425/
ixdp425_start.S 59 mrc p15, 0, r2, c1, c0, 0
62 mcr p15, 0, r2, c1, c0, 0
140 mcr p15, 0, r0, c2, c0, 0
147 mcr p15, 0, r0, c3, c0, 0
154 mrc p15, 0, r2, c1, c0, 0
157 mcr p15, 0, r2, c1, c0, 0
164 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */
  /src/sys/arch/evbarm/nslu2/
nslu2_start.S 55 mrc p15, 0, r2, c1, c0, 0
58 mcr p15, 0, r2, c1, c0, 0
136 mcr p15, 0, r0, c2, c0, 0
143 mcr p15, 0, r0, c3, c0, 0
150 mrc p15, 0, r2, c1, c0, 0
153 mcr p15, 0, r2, c1, c0, 0
160 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */

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