| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| intel_pm.c | 444 mutex_lock(&dev_priv->wm.wm_mutex);
447 dev_priv->wm.vlv.cxsr = enable;
449 dev_priv->wm.g4x.cxsr = enable;
450 mutex_unlock(&dev_priv->wm.wm_mutex);
478 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
741 * @wm: chip FIFO params
758 const struct intel_watermark_params *wm,
772 entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
773 wm->guard_size;
780 if (wm_size > wm->max_wm
876 unsigned int wm; local in function:pnv_update_wm
1130 unsigned int clock, htotal, cpp, width, wm; local in function:g4x_compute_wm
1240 int wm, max_wm; local in function:g4x_raw_plane_wm_compute
1640 unsigned int clock, htotal, cpp, width, wm; local in function:vlv_compute_wm_level
1820 int wm = vlv_compute_wm_level(crtc_state, plane_state, level); local in function:vlv_raw_plane_wm_compute
3199 struct intel_wm_level *wm = &pipe_wm->wm[level]; local in function:ilk_compute_pipe_wm
3292 const struct intel_wm_level *wm = &active->wm[level]; local in function:ilk_merge_wm_level
3333 struct intel_wm_level *wm = &merged->wm[level]; local in function:ilk_wm_merge
3363 struct intel_wm_level *wm = &merged->wm[level]; local in function:ilk_wm_merge
3845 struct skl_plane_wm *wm = local in function:intel_can_enable_sagv
4005 struct skl_wm_level wm = {}; local in function:skl_cursor_allocation
4348 const struct skl_plane_wm *wm = local in function:skl_allocate_pipe_ddb
4384 const struct skl_plane_wm *wm = local in function:skl_allocate_pipe_ddb
4456 struct skl_plane_wm *wm = local in function:skl_allocate_pipe_ddb
4493 struct skl_plane_wm *wm = local in function:skl_allocate_pipe_ddb
4937 struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; local in function:skl_build_plane_wm_single
4956 struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; local in function:skl_build_plane_wm_uv
5099 const struct skl_plane_wm *wm = local in function:skl_write_plane_wm
5135 const struct skl_plane_wm *wm = local in function:skl_write_cursor_wm
5609 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk; local in function:ilk_compute_wm_config
5703 struct skl_plane_wm *wm = &out->planes[plane_id]; local in function:skl_pipe_wm_get_hw_state
5911 struct g4x_wm_values *wm = &dev_priv->wm.g4x; local in function:g4x_wm_get_hw_state
6054 struct vlv_wm_values *wm = &dev_priv->wm.vlv; local in function:vlv_wm_get_hw_state
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| wm8750-apc8750.dts | 21 wm,pins = <168 169 170 171>;
22 wm,function = <2>; /* alt */
23 wm,pull = <2>; /* pull-up */
|
| wm8650.dtsi | 11 compatible = "wm,wm8650";
57 compatible = "wm,wm8650-pinctrl";
87 compatible = "wm,wm8650-pll-clock";
94 compatible = "wm,wm8650-pll-clock";
101 compatible = "wm,wm8650-pll-clock";
108 compatible = "wm,wm8650-pll-clock";
115 compatible = "wm,wm8650-pll-clock";
195 compatible = "wm,wm8505-sdhc";
204 compatible = "wm,wm8505-fb";
209 compatible = "wm,prizm-ge-rops"
[all...] |
| wm8850.dtsi | 11 compatible = "wm,wm8850";
60 compatible = "wm,wm8850-pinctrl";
90 compatible = "wm,wm8850-pll-clock";
97 compatible = "wm,wm8850-pll-clock";
104 compatible = "wm,wm8850-pll-clock";
111 compatible = "wm,wm8850-pll-clock";
118 compatible = "wm,wm8850-pll-clock";
125 compatible = "wm,wm8850-pll-clock";
132 compatible = "wm,wm8850-pll-clock";
219 compatible = "wm,wm8505-fb"
[all...] |
| wm8750.dtsi | 11 compatible = "wm,wm8750";
63 compatible = "wm,wm8750-pinctrl";
93 compatible = "wm,wm8750-pll-clock";
100 compatible = "wm,wm8750-pll-clock";
107 compatible = "wm,wm8750-pll-clock";
114 compatible = "wm,wm8750-pll-clock";
121 compatible = "wm,wm8750-pll-clock";
327 compatible = "wm,wm8505-sdhc";
336 compatible = "wm,wm8505-i2c";
344 compatible = "wm,wm8505-i2c"
[all...] |
| wm8505.dtsi | 11 compatible = "wm,wm8505";
61 compatible = "wm,wm8505-pinctrl";
223 compatible = "wm,wm8505-fb";
228 compatible = "wm,prizm-ge-rops";
287 compatible = "wm,wm8505-sdhc";
|
| /src/sbin/wdogctl/ |
| wdogctl.c | 190 struct wdog_mode wm; local in function:enable_kernel
193 prep_wmode(&wm, WDOG_MODE_KTICKLE, name, period);
199 if (ioctl(fd, WDOGIOC_SMODE, &wm) == -1)
208 struct wdog_mode wm; local in function:enable_ext
211 prep_wmode(&wm, WDOG_MODE_ETICKLE, name, period);
216 if (ioctl(fd, WDOGIOC_SMODE, &wm) == -1) {
221 wm.wm_name);
230 struct wdog_mode wm; local in function:enable_user
235 prep_wmode(&wm,
255 if (ioctl(fd, WDOGIOC_SMODE, &wm) == -1)
328 struct wdog_mode wm; local in function:disable
367 struct wdog_mode wm; local in function:list_timers
[all...] |
| /src/tests/dev/sysmon/ |
| t_swwdog.c | 68 struct wdog_mode wm; local in function:testbody
103 strlcpy(wm.wm_name, wc.wc_names, sizeof(wm.wm_name));
104 wm.wm_mode = WDOG_MODE_ETICKLE;
105 wm.wm_period = 1;
106 if (rump_sys_ioctl(fd, WDOGIOC_SMODE, &wm) == -1)
113 wm.wm_mode = WDOG_MODE_DISARMED;
114 rump_sys_ioctl(fd, WDOGIOC_SMODE, &wm);
|
| /src/sys/dev/sysmon/ |
| sysmon_wdog.c | 205 struct wdog_mode *wm = (void *) data; local in function:sysmonioctl_wdog
207 wm->wm_name[sizeof(wm->wm_name) - 1] = '\0';
208 smw = sysmon_wdog_find(wm->wm_name);
214 wm->wm_mode = smw->smw_mode;
215 wm->wm_period = smw->smw_period;
222 struct wdog_mode *wm = (void *) data; local in function:sysmonioctl_wdog
229 wm->wm_name[sizeof(wm->wm_name) - 1] = '\0';
230 smw = sysmon_wdog_find(wm->wm_name)
251 struct wdog_mode *wm = (void *) data; local in function:sysmonioctl_wdog
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_rs690.c | 279 struct rs690_watermark *wm,
291 wm->lb_request_fifo_depth = 4;
311 wm->num_line_pair.full = dfixed_const(2);
313 wm->num_line_pair.full = dfixed_const(1);
318 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
321 wm->lb_request_fifo_depth = 4;
323 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
348 wm->consumption_rate.full = dfixed_div(a, consumption_time);
366 wm->active_time.full = dfixed_mul(line_time, b);
367 wm->active_time.full = dfixed_div(wm->active_time, a)
[all...] |
| radeon_rv515.c | 962 struct rv515_watermark *wm,
974 wm->lb_request_fifo_depth = 4;
991 wm->num_line_pair.full = dfixed_const(2);
993 wm->num_line_pair.full = dfixed_const(1);
998 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
1001 wm->lb_request_fifo_depth = 4;
1003 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
1028 wm->consumption_rate.full = dfixed_div(a, consumption_time);
1046 wm->active_time.full = dfixed_mul(line_time, b);
1047 wm->active_time.full = dfixed_div(wm->active_time, a)
[all...] |
| radeon_si.c | 2080 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
2088 yclk.full = dfixed_const(wm->yclk);
2090 dram_channels.full = dfixed_const(wm->dram_channels * 4);
2100 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
2108 yclk.full = dfixed_const(wm->yclk);
2110 dram_channels.full = dfixed_const(wm->dram_channels * 4);
2120 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
2128 sclk.full = dfixed_const(wm->sclk);
2140 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
2145 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
[all...] |
| radeon_evergreen.c | 1952 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
1960 yclk.full = dfixed_const(wm->yclk);
1962 dram_channels.full = dfixed_const(wm->dram_channels * 4);
1972 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
1980 yclk.full = dfixed_const(wm->yclk);
1982 dram_channels.full = dfixed_const(wm->dram_channels * 4);
1992 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
2000 sclk.full = dfixed_const(wm->sclk);
2012 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
2020 disp_clk.full = dfixed_const(wm->disp_clk)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_atomic_plane.c | 336 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
339 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id],
345 entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
346 entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id];
388 memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y,
389 sizeof(old_crtc_state->wm.skl.plane_ddb_y));
390 memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv,
391 sizeof(old_crtc_state->wm.skl.plane_ddb_uv));
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dce_v10_0.c | 719 * @wm: watermark calculation data
725 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
733 yclk.full = dfixed_const(wm->yclk);
735 dram_channels.full = dfixed_const(wm->dram_channels * 4);
748 * @wm: watermark calculation data
754 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
762 yclk.full = dfixed_const(wm->yclk);
764 dram_channels.full = dfixed_const(wm->dram_channels * 4);
777 * @wm: watermark calculation data
783 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
[all...] |
| amdgpu_dce_v11_0.c | 745 * @wm: watermark calculation data
751 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
759 yclk.full = dfixed_const(wm->yclk);
761 dram_channels.full = dfixed_const(wm->dram_channels * 4);
774 * @wm: watermark calculation data
780 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
788 yclk.full = dfixed_const(wm->yclk);
790 dram_channels.full = dfixed_const(wm->dram_channels * 4);
803 * @wm: watermark calculation data
809 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
[all...] |
| amdgpu_dce_v6_0.c | 517 * @wm: watermark calculation data
523 static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm)
531 yclk.full = dfixed_const(wm->yclk);
533 dram_channels.full = dfixed_const(wm->dram_channels * 4);
546 * @wm: watermark calculation data
552 static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm)
560 yclk.full = dfixed_const(wm->yclk);
562 dram_channels.full = dfixed_const(wm->dram_channels * 4);
575 * @wm: watermark calculation data
581 static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm)
[all...] |
| amdgpu_dce_v8_0.c | 654 * @wm: watermark calculation data
660 static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
668 yclk.full = dfixed_const(wm->yclk);
670 dram_channels.full = dfixed_const(wm->dram_channels * 4);
683 * @wm: watermark calculation data
689 static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
697 yclk.full = dfixed_const(wm->yclk);
699 dram_channels.full = dfixed_const(wm->dram_channels * 4);
712 * @wm: watermark calculation data
718 static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hubbub.c | 485 struct dcn_hubbub_wm *wm)
491 memset(wm, 0, sizeof(struct dcn_hubbub_wm));
493 s = &wm->sets[0];
504 s = &wm->sets[1];
515 s = &wm->sets[2];
526 s = &wm->sets[3];
579 * for dcn1, all wm registers are 21-bit wide
|
| dcn20_hubbub.h | 126 struct dcn_hubbub_wm *wm);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| dchubbub.h | 133 struct dcn_hubbub_wm *wm);
|
| /src/sys/external/bsd/drm2/include/ |
| i915_trace.h | 528 "struct g4x_wm_values *"/*wm*/);
530 trace_g4x_wm(struct intel_crtc *crtc, const struct g4x_wm_values *wm)
532 TRACE2(i915,, g4x_wm, crtc, wm);
537 "struct vlv_wm_values *"/*wm*/);
539 trace_vlv_wm(struct intel_crtc *crtc, const struct vlv_wm_values *wm)
541 TRACE2(i915,, vlv_wm, crtc, wm);
|
| /src/sys/arch/evbarm/conf/ |
| GEMINI | 200 wm* at pci? dev ? function ? # Intel 8254x gigabit
|
| GEMINI_SLAVE | 217 wm* at pci? dev ? function ? # Intel 8254x gigabit
|
| /src/sys/arch/atari/dev/ |
| wdc_mb.c | 262 #define calc_addr(base, off, stride, wm) \
263 ((u_long)(base) + ((off) << (stride)) + (wm))
|
