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    Searched defs:data1 (Results 1 - 25 of 37) sorted by relevancy

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  /src/sys/arch/arm/apple/
apple_mbox.h 22 uint32_t data1; member in struct:apple_mbox_msg
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vf_error.c 59 u32 data1, data2, data3; local in function:amdgpu_vf_error_trans_all
82 data1 = AMDGIM_ERROR_CODE_FLAGS_TO_MAILBOX(adev->virt.vf_errors.code[index],
87 adev->virt.ops->trans_msg(adev, IDH_LOG_VF_ERROR, data1, data2, data3);
amdgpu_mmhub_v2_0.c 374 uint32_t def, data, def1, data1; local in function:mmhub_v2_0_update_medium_grain_clock_gating
378 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
383 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
393 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
404 if (def1 != data1)
405 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
448 int data, data1; local in function:mmhub_v2_0_get_clockgating
455 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
459 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
amdgpu_jpeg_v1_0.c 379 uint32_t data0, data1, mask; local in function:jpeg_v1_0_decode_ring_emit_vm_flush
385 data1 = lower_32_bits(pd_addr);
387 jpeg_v1_0_decode_ring_emit_reg_wait(ring, data0, data1, mask);
amdgpu_mmhub_v1_0.c 442 uint32_t def, data, def1, data1, def2 = 0, data2 = 0; local in function:mmhub_v1_0_update_medium_grain_clock_gating
447 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
450 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV);
455 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
472 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
491 if (def1 != data1) {
493 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
495 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1);
544 int data, data1; local in function:mmhub_v1_0_get_clockgating
551 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2)
    [all...]
amdgpu_mmhub_v9_4.c 548 uint32_t def, data, def1, data1; local in function:mmhub_v9_4_update_medium_grain_clock_gating
567 def1 = data1 = RREG32_SOC15_OFFSET(MMHUB, 0,
573 data1 &=
581 data1 |=
590 if (def1 != data1)
594 j * dist, data1);
646 int data, data1; local in function:mmhub_v9_4_get_clockgating
654 data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
657 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
amdgpu_uvd_v5_0.c 609 uint32_t data1, data3, suvd_flags; local in function:uvd_v5_0_enable_clock_gating
611 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
643 data1 |= suvd_flags;
646 data1 = 0;
649 WREG32(mmUVD_SUVD_CGC_GATE, data1);
703 uint32_t data, data1, cgc_flags, suvd_flags;
706 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
734 data1 |= suvd_flags;
737 WREG32(mmUVD_SUVD_CGC_GATE, data1);
amdgpu_jpeg_v2_0.c 633 uint32_t data0, data1, mask; local in function:jpeg_v2_0_dec_ring_emit_vm_flush
639 data1 = lower_32_bits(pd_addr);
641 jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
amdgpu_uvd_v6_0.c 622 u32 data, data1;
625 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
645 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
678 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
693 WREG32(mmUVD_SUVD_CGC_GATE, data1);
1255 uint32_t data1, data3; local in function:uvd_v6_0_enable_clock_gating
1257 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1260 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
1304 WREG32(mmUVD_SUVD_CGC_GATE, data1);
1359 uint32_t data, data1, cgc_flags, suvd_flags
    [all...]
amdgpu_uvd_v7_0.c 1381 uint32_t data0, data1, mask; local in function:uvd_v7_0_ring_emit_vm_flush
1387 data1 = lower_32_bits(pd_addr);
1389 uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask);
1590 uint32_t data, data1, data2, suvd_flags;
1593 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1636 data1 |= suvd_flags;
1640 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1646 uint32_t data, data1, cgc_flags, suvd_flags;
1649 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1679 data1 |= suvd_flags
    [all...]
amdgpu_vcn.h 162 unsigned data1; member in struct:amdgpu_vcn_reg
amdgpu_vcn_v1_0.c 145 adev->vcn.internal.data1 = adev->vcn.inst->external.data1 =
1547 uint32_t data0, data1, mask; local in function:vcn_v1_0_dec_ring_emit_vm_flush
1553 data1 = lower_32_bits(pd_addr);
1555 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
amdgpu_vcn_v2_0.c 154 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
155 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
1363 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1372 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1415 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1430 uint32_t data0, data1, mask; local in function:vcn_v2_0_dec_ring_emit_vm_flush
1436 data1 = lower_32_bits(pd_addr);
1438 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1449 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
  /src/sys/external/bsd/compiler_rt/dist/lib/tsan/tests/rtl/
tsan_string.cc 42 char *data1 = new char[10]; local in function:__tsan::TEST
45 t1.Memcpy(data, data1, 10);
51 char *data1 = new char[10]; local in function:__tsan::TEST
54 t1.Memcpy(data+5, data1, 1);
60 char *data1 = new char[10]; local in function:__tsan::TEST
63 t1.Memcpy(data, data1, 10);
64 t2.Memcpy(data1, data2, 10, true);
69 char *data1 = new char[10]; local in function:__tsan::TEST
71 t1.Memcpy(data, data1, 10);
72 t2.Memcpy(data, data1, 10, true)
    [all...]
  /src/sys/arch/x86/pci/
fwhrng.c 74 uint8_t id0, id1, data0, data1; local in function:fwhrng_match
84 data1 = bus_space_read_1(bst, bsh, 1);
93 data0, data1, id0, id1);
96 if ((id0 == data0) && (id1 == data1))
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pmu/
nouveau_nvkm_subdev_pmu_gt215.c 36 u32 process, u32 message, u32 data0, u32 data1)
74 nvkm_wr32(device, 0x10a1c4, data1);
99 u32 process, message, data0, data1; local in function:gt215_pmu_recv
117 data1 = nvkm_rd32(device, 0x10a1c4);
129 pmu->recv.data[1] = data1;
145 process, message, data0, data1);
  /src/sys/arch/macppc/dev/
ams.c 263 static u_char data1[] = local in function:ems_init
271 adb_op_sync((Ptr)data1, NULL, (Ptr)0, ADBLISTEN(adbaddr, 2));
  /src/sys/dev/acpi/wmi/
wmi_acpivar.h 59 uint32_t data1; member in struct:guid_t::__anon51c7cc390108
111 ((a)->data1 == (b)->data1 && \
  /src/sys/arch/hpcarm/dev/
uda1341.c 100 uint8_t data1; /* extended addressing register 2 */ member in struct:__anonc9cbf1340208
290 EXTEND_REG.data1 = EXT_DATA_COMMN | 0x4 ;
295 EXTEND_REG.data1 = EXT_DATA_COMMN | 0x4 ;
300 EXTEND_REG.data1 = EXT_DATA_COMMN | DATA_E2_MS(30);
305 EXTEND_REG.data1 = EXT_DATA_COMMN | DATA_E3_IG_L(0);
310 EXTEND_REG.data1 = EXT_DATA_COMMN | DATA_E4_IG_H(0);
315 EXTEND_REG.data1 = EXT_DATA_COMMN;
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/
nouveau_nvkm_engine_gr_ctxgk104.c 873 u32 data1 = nvkm_rd32(device, 0x17e920); local in function:gk104_grctx_generate_patch_ltc
876 mmio_wr32(info, 0x17e920, data1);
  /src/sys/arch/bebox/stand/boot/
ld.script 55 .data1 : { *(.data1) }
  /src/sys/arch/prep/stand/boot/
ld.script 55 .data1 : { *(.data1) }
  /src/sys/arch/rs6000/stand/boot/
ld.script 55 .data1 : { *(.data1) }
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_uvd.c 580 int data0, int data1,
591 idx = radeon_get_ib_value(p, data1);
604 p->ib.ptr[data1] = start >> 32;
657 int *data0, int *data1,
670 *data1 = p->idx;
673 r = radeon_uvd_cs_reloc(p, *data0, *data1,
694 int r, data0 = 0, data1 = 0; local in function:radeon_uvd_cs_parse
725 r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
  /src/sys/arch/sparc64/sparc64/
db_interface.c 489 unsigned long long i, j, k, data0, data1; local in function:db_dump_pmap
507 data1 = ldxa((vaddr_t)&ptbl[j], ASI_PHYS_CACHED);
508 if (!data0 && !data1) {
516 data1);

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