| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| radv_meta_dcc_retile.c | 172 &vk_pipeline_info, NULL, &device->meta_state.dcc_retile.pipeline[surf->u.gfx9.swizzle_mode]);
198 unsigned swizzle_mode = image->planes[0].surface.u.gfx9.swizzle_mode; local
201 if (!cmd_buffer->device->meta_state.dcc_retile.pipeline[swizzle_mode]) {
215 device->meta_state.dcc_retile.pipeline[swizzle_mode]);
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| radv_radeon_winsys.h | 145 unsigned swizzle_mode : 5; member in struct:radeon_bo_metadata::__anon582::__anon584
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/ |
| crocus_bufmgr.h | 106 uint32_t swizzle_mode; member in struct:crocus_bo
263 * \param swizzle_mode returned swizzling mode
266 uint32_t *swizzle_mode);
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| crocus_screen.c | 726 uint32_t swizzle_mode = 0; local
733 crocus_bo_get_tiling(buffer, &tiling, &swizzle_mode);
736 return swizzle_mode != I915_BIT_6_SWIZZLE_NONE;
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| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/ |
| brw_bufmgr.h | 168 uint32_t swizzle_mode; member in struct:brw_bo
320 * \param swizzle_mode returned swizzling mode
323 uint32_t *swizzle_mode);
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| brw_screen.c | 1936 uint32_t swizzle_mode = 0; local
1943 brw_bo_get_tiling(buffer, &tiling, &swizzle_mode);
1946 return swizzle_mode != I915_BIT_6_SWIZZLE_NONE;
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/iris/ |
| iris_bufmgr.h | 154 uint32_t swizzle_mode; member in struct:iris_bo
291 * \param swizzle_mode returned swizzling mode
294 uint32_t *swizzle_mode);
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| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/ |
| brw_bufmgr.h | 167 uint32_t swizzle_mode; member in struct:brw_bo
312 * \param swizzle_mode returned swizzling mode
315 uint32_t *swizzle_mode);
|
| intel_screen.c | 1928 uint32_t swizzle_mode = 0; local
1935 brw_bo_get_tiling(buffer, &tiling, &swizzle_mode);
1938 return swizzle_mode != I915_BIT_6_SWIZZLE_NONE;
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| /xsrc/external/mit/xf86-video-intel-old/dist/src/ |
| i830_uxa.c | 102 uint32_t tiling_mode, swizzle_mode; local
105 ret = drm_intel_bo_get_tiling(bo, &tiling_mode, &swizzle_mode);
|
| /xsrc/external/mit/MesaLib/dist/src/amd/common/ |
| ac_surface_meta_address_test.c | 59 /* equation varies with resource_type, swizzle_mode,
198 unsigned swizzle_mode, bool pipe_aligned, bool rb_aligned,
217 xin.swizzleMode = in.swizzleMode = din.swizzleMode = swizzle_mode;
321 unsigned swizzle_mode = info->chip_class == GFX9 ? ADDR_SW_64KB_S_X : ADDR_SW_64KB_R_X; local
363 bpp, swizzle_mode, pipe_aligned, rb_aligned, mrt_index,
405 unsigned bpp, unsigned swizzle_mode,
424 hin.swizzleMode = in.swizzleMode = xin.swizzleMode = swizzle_mode;
544 unsigned bpp, unsigned swizzle_mode,
557 cin.swizzleMode = xin.swizzleMode = in.swizzleMode = swizzle_mode;
640 unsigned swizzle_mode = info->chip_class == GFX9 ? ADDR_SW_64KB_S_X : ADDR_SW_64KB_Z_X local
[all...] |
| ac_surface.h | 198 * - swizzle_mode
232 uint8_t swizzle_mode; /* color or depth */ member in struct:gfx9_surf_layout
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/ |
| si_compute_blit.c | 623 void **shader = &sctx->cs_dcc_retile[tex->surface.u.gfx9.swizzle_mode];
667 unsigned swizzle_mode = tex->surface.u.gfx9.swizzle_mode; local
672 void **shader = &sctx->cs_clear_dcc_msaa[swizzle_mode][bpe_log2][fragments8][log2_samples - 2][is_array];
|
| /xsrc/external/mit/xf86-video-intel/dist/src/uxa/ |
| intel_uxa.c | 612 uint32_t tiling, swizzle_mode; local
625 if (drm_intel_bo_get_tiling(bo, &tiling, &swizzle_mode)) {
|
| /xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/ |
| intel_uxa.c | 587 uint32_t tiling, swizzle_mode; local
600 if (drm_intel_bo_get_tiling(bo, &tiling, &swizzle_mode)) {
|
| /xsrc/external/mit/MesaLib.old/dist/src/amd/common/ |
| ac_surface.h | 128 uint16_t swizzle_mode; /* tile mode */ member in struct:gfx9_surf_flags
|
| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| radv_radeon_winsys.h | 153 unsigned swizzle_mode:5; member in struct:radeon_bo_metadata::__anon3266::__anon3268
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/ |
| radeon_winsys.h | 220 unsigned swizzle_mode:5; member in struct:radeon_bo_metadata::__anon4022::__anon4024
|
| radeon_uvd_enc.h | 323 uint32_t swizzle_mode; member in union:ruvd_enc_encode_context_buffer_s::__anon4006
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| radeon_vcn_enc.h | 349 uint32_t swizzle_mode; member in struct:rvcn_enc_encode_context_buffer_s
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/ |
| radeon_uvd_enc.h | 296 uint32_t swizzle_mode; member in union:ruvd_enc_encode_context_buffer_s::__anon1532
|
| radeon_vcn_enc.h | 349 uint32_t swizzle_mode; member in struct:rvcn_enc_encode_context_buffer_s
|
| /xsrc/external/mit/libdrm/dist/intel/ |
| intel_bufmgr_gem.c | 191 uint32_t swizzle_mode; member in struct:_drm_intel_bo_gem
293 uint32_t * swizzle_mode);
783 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
944 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
1036 uint32_t *swizzle_mode)
1050 *swizzle_mode = get_tiling.swizzle_mode;
1132 &bo_gem->tiling_mode, &bo_gem->swizzle_mode);
2518 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
[all...] |
| /xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/ |
| kgem.c | 1363 uint32_t swizzle_mode; member in struct:local_i915_gem_get_tiling_v2
1379 if (kgem->gen < 50 && tiling.phys_swizzle_mode != tiling.swizzle_mode)
1382 choose_memcpy_tiled_x(kgem, tiling.swizzle_mode);
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| /xsrc/external/mit/MesaLib.old/dist/include/drm-uapi/ |
| i915_drm.h | 1243 __u32 swizzle_mode; member in struct:drm_i915_gem_set_tiling
1260 __u32 swizzle_mode; member in struct:drm_i915_gem_get_tiling
|
