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    Searched refs:ACPILevel (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 1317 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1322 table->ACPILevel.SclkFrequency =
1326 table->ACPILevel.SclkFrequency,
1327 (uint32_t *)(&table->ACPILevel.MinVoltage), &mvdd);
1333 table->ACPILevel.SclkFrequency =
1335 table->ACPILevel.MinVoltage =
1341 table->ACPILevel.SclkFrequency, &dividers);
1346 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1347 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1348 table->ACPILevel.DeepSleepDivId = 0
    [all...]
amdgpu_iceland_smumgr.c 1443 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1446 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
1448 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);
1450 table->ACPILevel.MinVddcPhases = vddc_phase_shed_control ? 0 : 1;
1452 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
1456 table->ACPILevel.SclkFrequency, &dividers);
1462 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1463 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1464 table->ACPILevel.DeepSleepDivId = 0;
1473 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl
    [all...]
amdgpu_vegam_smumgr.c 1123 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1131 &table->ACPILevel.MinVoltage, &mvdd);
1138 &(table->ACPILevel.SclkSetting));
1143 table->ACPILevel.DeepSleepDivId = 0;
1144 table->ACPILevel.CcPwrDynRm = 0;
1145 table->ACPILevel.CcPwrDynRm1 = 0;
1147 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1148 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1149 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1150 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1)
    [all...]
amdgpu_ci_smumgr.c 1395 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1398 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
1400 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);
1402 table->ACPILevel.MinVddcPhases = data->vddc_phase_shed_control ? 0 : 1;
1404 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
1408 table->ACPILevel.SclkFrequency, &dividers);
1414 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1415 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1416 table->ACPILevel.DeepSleepDivId = 0;
1425 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl
    [all...]
amdgpu_tonga_smumgr.c 1194 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1196 table->ACPILevel.MinVoltage =
1200 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
1204 table->ACPILevel.SclkFrequency, &dividers);
1211 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1212 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1213 table->ACPILevel.DeepSleepDivId = 0;
1222 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
1223 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
1224 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3
    [all...]
amdgpu_polaris10_smumgr.c 1215 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1223 &table->ACPILevel.MinVoltage, &mvdd);
1229 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
1232 table->ACPILevel.DeepSleepDivId = 0;
1233 table->ACPILevel.CcPwrDynRm = 0;
1234 table->ACPILevel.CcPwrDynRm1 = 0;
1236 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1237 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1238 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1239 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_ci_dpm.c 3007 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
3010 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
3012 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
3014 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
3016 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
3020 table->ACPILevel.SclkFrequency, false, &dividers);
3024 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
3025 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3026 table->ACPILevel.DeepSleepDivId = 0;
3034 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl
    [all...]
smu7_fusion.h 236 SMU7_Fusion_ACPILevel ACPILevel;
smu7_discrete.h 328 SMU7_Discrete_ACPILevel ACPILevel;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu7_fusion.h 236 SMU7_Fusion_ACPILevel ACPILevel;
smu71_discrete.h 276 SMU71_Discrete_ACPILevel ACPILevel;
smu7_discrete.h 329 SMU7_Discrete_ACPILevel ACPILevel;
smu72_discrete.h 271 SMU72_Discrete_ACPILevel ACPILevel;
smu73_discrete.h 255 SMU73_Discrete_ACPILevel ACPILevel;
smu74_discrete.h 287 SMU74_Discrete_ACPILevel ACPILevel;
smu75_discrete.h 293 SMU75_Discrete_ACPILevel ACPILevel;

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