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    Searched refs:GraphicsLevel (Results 1 - 18 of 18) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu7_fusion.h 235 SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE];
smu71_discrete.h 213 // Use this instead of copies of the GraphicsLevel and MemoryLevel structures to keep track of state parameters
272 SMU71_Discrete_GraphicsLevel GraphicsLevel [SMU71_MAX_LEVELS_GRAPHICS];
smu7_discrete.h 325 SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS];
smu72_discrete.h 267 SMU72_Discrete_GraphicsLevel GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS];
smu73_discrete.h 251 SMU73_Discrete_GraphicsLevel GraphicsLevel [SMU73_MAX_LEVELS_GRAPHICS];
smu74_discrete.h 283 SMU74_Discrete_GraphicsLevel GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS];
smu75_discrete.h 289 SMU75_Discrete_GraphicsLevel GraphicsLevel [SMU75_MAX_LEVELS_GRAPHICS];
  /src/sys/external/bsd/drm2/dist/drm/radeon/
smu7_fusion.h 235 SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE];
smu7_discrete.h 324 SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS];
radeon_ci_dpm.c 3287 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3290 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3299 &pi->smc_state_table.GraphicsLevel[i]);
3303 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3305 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3308 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
radeon_kv_dpm.c 776 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
1788 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_tonga_smumgr.c 700 offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
705 SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
718 &(smu_data->smc_state_table.GraphicsLevel[i]));
724 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
728 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
732 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
746 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
776 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
779 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
782 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled
    [all...]
amdgpu_iceland_smumgr.c 970 offsetof(SMU71_Discrete_DpmTable, GraphicsLevel);
975 SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
988 &(smu_data->smc_state_table.GraphicsLevel[i]));
994 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
998 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1002 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
1032 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
1036 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
1039 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
amdgpu_fiji_smumgr.c 256 level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
1018 offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
1022 smu_data->smc_state_table.GraphicsLevel;
1753 GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1].
1797 smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency);
2559 smu_data->smc_state_table.GraphicsLevel;
2561 offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
amdgpu_polaris10_smumgr.c 151 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
993 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
997 smu_data->smc_state_table.GraphicsLevel;
1010 &(smu_data->smc_state_table.GraphicsLevel[i]));
1020 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1022 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
2475 smu_data->smc_state_table.GraphicsLevel;
2477 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
amdgpu_ci_smumgr.c 482 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
486 smu_data->smc_state_table.GraphicsLevel;
496 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
498 smu_data->smc_state_table.GraphicsLevel[i].DisplayWatermark =
502 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
2770 smu_data->smc_state_table.GraphicsLevel;
2772 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
amdgpu_vegam_smumgr.c 877 offsetof(SMU75_Discrete_DpmTable, GraphicsLevel);
881 smu_data->smc_state_table.GraphicsLevel;
894 &(smu_data->smc_state_table.GraphicsLevel[i]));
908 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_kv_dpm.c 859 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
1852 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +

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