| /src/sys/external/isc/atheros_hal/dist/ar5212/ |
| ar5212_beacon.c | 164 | SM(bs->bs_intval, AR_BEACON_PERIOD)
165 | SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)
175 | SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR);
229 SM((nextdtim - SLEEP_SLOP) << 3, AR_SLEEP1_NEXT_DTIM)
230 | SM(CAB_TIMEOUT_VAL, AR_SLEEP1_CAB_TIMEOUT)
235 SM((nextTbtt - SLEEP_SLOP) << 3, AR_SLEEP2_NEXT_TIM)
236 | SM(BEACON_TIMEOUT_VAL, AR_SLEEP2_BEACON_TIMEOUT)
239 SM(beaconintval, AR_SLEEP3_TIM_PERIOD)
240 | SM(dtimperiod, AR_SLEEP3_DTIM_PERIOD)
|
| ar5212_xmit.c | 70 (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG));
215 SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
216 | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)
219 SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
220 | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)
306 SM(cwMin, AR_D_LCL_IFS_CWMIN)
307 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
308 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
312 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH)
313 | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG
[all...] |
| ar2316.c | 537 pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),
557 | SM(numPdGainsUsed-1, AR_PHY_TPCRG1_NUM_PD_GAIN);
561 tpcrg1 |= SM(rfXpdGain[2], AR_PHY_TPCRG1_PDGAIN_SETTING3);
565 tpcrg1 |= SM(rfXpdGain[1], AR_PHY_TPCRG1_PDGAIN_SETTING2);
569 tpcrg1 |= SM(rfXpdGain[0], AR_PHY_TPCRG1_PDGAIN_SETTING1);
603 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
604 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
605 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
606 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
607 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4))
[all...] |
| ar2317.c | 515 pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),
535 | SM(numPdGainsUsed-1, AR_PHY_TPCRG1_NUM_PD_GAIN);
539 tpcrg1 |= SM(rfXpdGain[2], AR_PHY_TPCRG1_PDGAIN_SETTING3);
543 tpcrg1 |= SM(rfXpdGain[1], AR_PHY_TPCRG1_PDGAIN_SETTING2);
547 tpcrg1 |= SM(rfXpdGain[0], AR_PHY_TPCRG1_PDGAIN_SETTING1);
581 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
582 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
583 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
584 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
585 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4))
[all...] |
| ar2413.c | 531 pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),
551 | SM(numPdGainsUsed-1, AR_PHY_TPCRG1_NUM_PD_GAIN);
555 tpcrg1 |= SM(rfXpdGain[2], AR_PHY_TPCRG1_PDGAIN_SETTING3);
559 tpcrg1 |= SM(rfXpdGain[1], AR_PHY_TPCRG1_PDGAIN_SETTING2);
563 tpcrg1 |= SM(rfXpdGain[0], AR_PHY_TPCRG1_PDGAIN_SETTING1);
597 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
598 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
599 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
600 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
601 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4))
[all...] |
| ar5413.c | 567 pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),
587 | SM(numPdGainsUsed-1, AR_PHY_TPCRG1_NUM_PD_GAIN);
591 tpcrg1 |= SM(rfXpdGain[2], AR_PHY_TPCRG1_PDGAIN_SETTING3);
595 tpcrg1 |= SM(rfXpdGain[1], AR_PHY_TPCRG1_PDGAIN_SETTING2);
599 tpcrg1 |= SM(rfXpdGain[0], AR_PHY_TPCRG1_PDGAIN_SETTING1);
633 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
634 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
635 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
636 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
637 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4))
[all...] |
| /src/sys/external/isc/atheros_hal/dist/ar5416/ |
| ar5416_xmit.c | 79 SM(10, AR_QUIET2_QUIET_DUR));
125 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
128 (SM((_series)[_index].Rate, AR_XmitRate##_index))
131 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) |\
138 |SM((_series)[_index].ChSel, AR_ChainSel##_index)
196 ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0)
204 ads->ds_ctl7 = SM(ahp->ah_tx_chainmask, AR_ChainSel0)
205 | SM(ahp->ah_tx_chainmask, AR_ChainSel1)
206 | SM(ahp->ah_tx_chainmask, AR_ChainSel2)
207 | SM(ahp->ah_tx_chainmask, AR_ChainSel3
[all...] |
| ar5416_reset.c | 352 powerVal = SM(ackTpcPow, AR_TPC_ACK) |
353 SM(ctsTpcPow, AR_TPC_CTS) |
354 SM(chirpTpcPow, AR_TPC_CHIRP);
509 SM(ahp->ah_txTrigLev, AR_FTRIG));
604 SM(2, AR_NOACK_2BIT_VALUE) |
605 SM(5, AR_NOACK_BIT_OFFSET) |
606 SM(0, AR_NOACK_BYTE_OFFSET));
1188 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
1191 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
1193 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL)
[all...] |
| ar5416_beacon.c | 224 SM((CAB_TIMEOUT_VAL << 3), AR5416_SLEEP1_CAB_TIMEOUT)
228 SM((BEACON_TIMEOUT_VAL << 3), AR5416_SLEEP2_BEACON_TIMEOUT));
|
| ar9285_reset.c | 262 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
263 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
593 SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) |
594 SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(0, AR_PHY_TPCRG1_PD_GAIN_3));
625 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
626 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
627 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
628 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
[all...] |
| ar5416_misc.c | 78 | SM(AR_MAC_LED_MODE_POWON, AR_MAC_LED_MODE)
80 | SM(AR_MAC_LED_MODE_NETON, AR_MAC_LED_MODE)
84 | SM(ledbits[state & 0x7], AR_MAC_LED_ASSOC);
|
| /src/sys/external/isc/atheros_hal/dist/ar5210/ |
| ar5210_beacon.c | 147 | SM(bs->bs_intval, AR_BEACON_PERIOD)
148 | SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)
186 | SM(bs->bs_bmissthreshold > BMISS_MAX ?
|
| /src/sys/external/isc/atheros_hal/dist/ar5211/ |
| ar5211_beacon.c | 154 | SM(bs->bs_intval, AR_BEACON_PERIOD)
155 | SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)
165 | SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR);
|
| ar5211_xmit.c | 183 SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
184 | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)
187 SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
188 | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)
269 SM(cwMin, AR_D_LCL_IFS_CWMIN)
270 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
271 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
275 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH)
276 | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG)
277 | SM(qi->tqi_lgretry, AR_D_RETRY_LIMIT_FR_LG
[all...] |
| /src/usr.bin/rdist/ |
| gram.y | 57 %term SM 4
142 cmd: INSTALL options opt_namelist SM = {
158 | NOTIFY namelist SM = {
163 | EXCEPT namelist SM = {
168 | PATTERN namelist SM = {
173 | SPECIAL opt_namelist STRING SM = {
239 case ';': /* SM */
240 return(SM);
|
| defs.h | 60 #define SM 4
|
| /src/sys/external/isc/atheros_hal/dist/ar5312/ |
| ar5312_reset.c | 267 SM(2, AR_PHY_ADC_CTL_OFF_INBUFGAIN) |
268 SM(2, AR_PHY_ADC_CTL_ON_INBUFGAIN) |
281 SM((ee->ee_cckOfdmPwrDelta*-1), AR_PHY_TXPWRADJ_CCK_GAIN_DELTA) |
282 SM((cckOfdmPwrDelta*-1), AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX));
313 SM(2, AR_PHY_SIGMA_DELTA_ADC_SEL) |
314 SM(4, AR_PHY_SIGMA_DELTA_FILT2) |
315 SM(0x16, AR_PHY_SIGMA_DELTA_FILT1) |
316 SM(0, AR_PHY_SIGMA_DELTA_ADC_CLIP));
566 SM(2, AR_NOACK_2BIT_VALUE) |
567 SM(5, AR_NOACK_BIT_OFFSET)
[all...] |
| ar5312_misc.c | 43 val = SM(AR5312_PCICFG_LEDSEL0, AR5312_PCICFG_LEDSEL) |
44 SM(AR5312_PCICFG_LEDMOD0, AR5312_PCICFG_LEDMODE) |
|
| /src/sys/dev/ic/ |
| arn5416.c | 198 phy |= SM(AR5416_AMODE_REFSEL, 2);
204 phy |= SM(AR5416_AMODE_REFSEL, 1);
206 phy |= SM(AR5416_AMODE_REFSEL, 2);
210 phy |= SM(AR5416_AMODE_REFSEL, 2);
287 reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
288 reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
289 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
290 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
493 reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP,
495 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1
[all...] |
| arn9003.c | 962 AR_RXI_CTRL_STAT)) != SM(AR_RXI_DESC_ID, AR_VENDOR_ATHEROS))
1115 (SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | AR_TXI_DESC_TX)) {
1273 SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) |
1274 SM(AR_TXI_DESC_NDWORDS, 23) |
1275 SM(AR_TXI_QCU_NUM, ATHN_QID_BEACON) |
1279 ds->ds_ctl11 = SM(AR_TXC11_FRAME_LEN, totlen);
1280 ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, AR_MAX_RATE_POWER);
1281 ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, AR_FRAME_TYPE_BEACON);
1283 ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, AR_ENCR_TYPE_CLEAR);
1286 ds->ds_ctl13 = SM(AR_TXC13_XMIT_DATA_TRIES0, 1)
[all...] |
| athn.c | 797 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5);
798 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c);
800 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05);
807 pll |= SM(AR_RTC_9160_PLL_DIV, 0x28);
809 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c);
811 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05);
813 pll |= SM(AR_RTC_9160_PLL_DIV, 0x50);
815 pll |= SM(AR_RTC_9160_PLL_DIV, 0x58);
819 pll |= SM(AR_RTC_PLL_DIV, 0x0a);
821 pll |= SM(AR_RTC_PLL_DIV, 0x0b)
[all...] |
| arn9280.c | 205 phy |= SM(AR9280_AMODE_REFSEL, 3);
209 phy |= SM(AR9280_AMODE_REFSEL, 2);
350 reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
351 reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
352 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
353 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
506 SM(AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_SPUR_RSSI_THRESH));
534 SM(AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd) |
535 SM(AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase));
538 SM(AR_PHY_SFCORR_SPUR_SUBCHNL_SD, spur_subchannel_sd))
[all...] |
| /src/sys/dev/pci/ |
| if_rtwn.c | 465 desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) |
833 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
871 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) |
872 SM(R92C_LLT_INIT_ADDR, addr) |
873 SM(R92C_LLT_INIT_DATA, data));
1582 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) |
1583 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) |
1584 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) |
1585 SM(R92C_EDCA_PARAM_AIFS, aifs))
[all...] |
| /src/sys/dev/usb/ |
| if_urtwn.c | 1212 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
1221 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
1230 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
1272 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) |
1273 SM(R92C_LLT_INIT_ADDR, addr) |
1274 SM(R92C_LLT_INIT_DATA, data));
2282 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit)
[all...] |
| /src/sys/dev/mii/ |
| mvphy.c | 71 #define SM(_v, _f) (((_v) << _f##_S) & _f)
203 SM(MV_ATUCTRL_AGE_TIME_DEFAULT, MV_ATUCTRL_AGE_TIME)
204 | SM(MV_ATUCTRL_ATU_SIZE_DEFAULT, MV_ATUCTRL_ATU_SIZE));
|
