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  /src/sys/arch/arm/nxp/
imx6_usbreg.h 37 #define USBC_UOG_USBMODE_SDIS __BIT(4)
38 #define USBC_UOG_USBMODE_SLOM __BIT(3)
39 #define USBC_UOG_USBMODE_ES __BIT(2)
44 #define USBC_UH_PORTSC1_PE __BIT(2)
45 #define USBC_UH_PORTSC1_PTS_2 __BIT(25)
46 #define USBC_UH_PORTSC1_PTS_MASK (__BITS(31, 30) | __BIT(25))
48 #define USBC_UH_PORTSC1_PTS_ULPI __BIT(31)
49 #define USBC_UH_PORTSC1_PTS_SERIAL (__BIT(31) | __BIT(30))
50 #define USBC_UH_PORTSC1_PTS_HSIC __BIT(25
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imx6_srcreg.h 36 #define SRC_SCR_DBG_RST_MASK_PG __BIT(25)
38 #define SRC_SCR_COREN_ENABLE(n) __BIT(22 + ((n) - 1)) /* no core0 bit */
39 #define SRC_SCR_CORE3_ENABLE __BIT(24)
40 #define SRC_SCR_CORE2_ENABLE __BIT(23)
41 #define SRC_SCR_CORE1_ENABLE __BIT(22)
42 #define SRC_SCR_CORES_DBG_RST __BIT(21)
43 #define SRC_SCR_COREN_DBG_RST(n) __BIT(17 + (n))
44 #define SRC_SCR_CORE3_DBG_RST __BIT(20)
45 #define SRC_SCR_CORE2_DBG_RST __BIT(19)
46 #define SRC_SCR_CORE1_DBG_RST __BIT(18
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  /src/sys/dev/pci/qat/
qat_c62xreg.h 76 #define SOFTSTRAP_SS_POWERGATE_CY_C62X __BIT(23)
77 #define SOFTSTRAP_SS_POWERGATE_PKE_C62X __BIT(24)
91 #define ENABLE_AE_ECC_ERR_C62X __BIT(28)
92 #define ENABLE_AE_ECC_PARITY_CORR_C62X (__BIT(24) | __BIT(12))
93 #define ERRSSMSH_EN_C62X __BIT(3)
95 #define PPERR_EN_C62X (__BIT(2))
103 #define ERRMSK0_CERR_C62X (__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0)
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qat_d15xxreg.h 76 #define SOFTSTRAP_SS_POWERGATE_CY_D15XX __BIT(23)
77 #define SOFTSTRAP_SS_POWERGATE_PKE_D15XX __BIT(24)
91 #define ENABLE_AE_ECC_ERR_D15XX __BIT(28)
92 #define ENABLE_AE_ECC_PARITY_CORR_D15XX (__BIT(24) | __BIT(12))
93 #define ERRSSMSH_EN_D15XX __BIT(3)
95 #define PPERR_EN_D15XX (__BIT(2))
103 #define ERRMSK0_CERR_D15XX (__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0)
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qat_c3xxxreg.h 76 #define SOFTSTRAP_SS_POWERGATE_CY_C3XXX __BIT(23)
77 #define SOFTSTRAP_SS_POWERGATE_PKE_C3XXX __BIT(24)
91 #define ENABLE_AE_ECC_ERR_C3XXX __BIT(28)
92 #define ENABLE_AE_ECC_PARITY_CORR_C3XXX (__BIT(24) | __BIT(12))
93 #define ERRSSMSH_EN_C3XXX __BIT(3)
95 #define PPERR_EN_C3XXX (__BIT(2))
103 #define ERRMSK0_CERR_C3XXX (__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0)
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  /src/sys/arch/arm/sunxi/
sunxi_mmc.h 64 #define SUNXI_MMC_GCTRL_ACCESS_BY_AHB __BIT(31)
65 #define SUNXI_MMC_GCTRL_WAIT_MEM_ACCESS_DONE __BIT(30)
66 #define SUNXI_MMC_GCTRL_DDR_MODE __BIT(10)
67 #define SUNXI_MMC_GCTRL_DEBOUNCEEN __BIT(8)
68 #define SUNXI_MMC_GCTRL_DMAEN __BIT(5)
69 #define SUNXI_MMC_GCTRL_INTEN __BIT(4)
70 #define SUNXI_MMC_GCTRL_DMARESET __BIT(2)
71 #define SUNXI_MMC_GCTRL_FIFORESET __BIT(1)
72 #define SUNXI_MMC_GCTRL_SOFTRESET __BIT(0)
76 #define SUNXI_MMC_CLKCR_MASK_DATA0 __BIT(31
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sun4i_spireg.h 39 #define SPI_CTL_SDM __BIT(20)
40 #define SPI_CTL_SDC __BIT(19)
41 #define SPI_CTL_TP_EN __BIT(18)
42 #define SPI_CTL_SS_LEVEL __BIT(17)
43 #define SPI_CTL_SS_CTRL __BIT(16)
44 #define SPI_CTL_DHB __BIT(15)
45 #define SPI_CTL_DDB __BIT(14)
47 #define SPI_CTL_RPSM __BIT(11)
48 #define SPI_CTL_XCH __BIT(10)
49 #define SPI_CTL_RF_RST __BIT(9
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sun6i_spireg.h 35 #define SPI_GCR_SRST __BIT(31)
36 #define SPI_GCR_TP_EN __BIT(7)
37 #define SPI_GCR_MODE __BIT(1)
40 #define SPI_GCR_EN __BIT(0)
43 #define SPI_TCR_XCH __BIT(31)
44 #define SPI_TCR_SDDM __BIT(14)
45 #define SPI_TCR_SDM __BIT(13)
46 #define SPI_TCR_FBS __BIT(12)
47 #define SPI_TCR_SDC __BIT(11)
48 #define SPI_TCR_RPSM __BIT(10
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  /src/sys/arch/arm/imx/
imxwdogreg.h 55 #define WCR_WDZST __BIT(0) /* watchdog low power */
56 #define WCR_WDBG __BIT(1) /* watchdog debug enable */
57 #define WCR_WDE __BIT(2) /* watchdog enable */
58 #define WCR_WDT __BIT(3) /* timeout assertion */
59 #define WCR_SRS __BIT(4) /* software reset signal */
60 #define WCR_WDA __BIT(5) /* ipp_wdog* assertion */
61 #define WCR_WDW __BIT(7) /* disable for wait */
71 #define WRSR_SFTW __BIT(0) /* reset is the result of a
73 #define WRSR_TOUT __BIT(1) /* reset is the result of a
76 #define WRSR_CMON __BIT(2
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imx23_uartdbgreg.h 51 #define HW_UARTDBGDR_OE __BIT(11)
52 #define HW_UARTDBGDR_BE __BIT(10)
53 #define HW_UARTDBGDR_PE __BIT(9)
54 #define HW_UARTDBGDR_FE __BIT(8)
64 #define HW_UARTDBGRSR_ECR_OE __BIT(3)
65 #define HW_UARTDBGRSR_ECR_BE __BIT(2)
66 #define HW_UARTDBGRSR_ECR_PE __BIT(1)
67 #define HW_UARTDBGRSR_ECR_FE __BIT(0)
76 #define HW_UARTDBGFR_RI __BIT(8)
77 #define HW_UARTDBGFR_TXFE __BIT(7
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imxusbreg.h 36 #define HWHOST_HC __BIT(0)
39 #define HWDEVICE_DC __BIT(0)
47 #define ULPI_WU __BIT(31)
48 #define ULPI_RUN __BIT(30)
49 #define ULPI_RW __BIT(29)
50 #define ULPI_SS __BIT(27)
57 #define OTGSC_DPIE __BIT(30)
58 #define OTGSC_1MSE __BIT(29)
59 #define OTGSC_BSEIE __BIT(28)
60 #define OTGSC_BSVIE __BIT(27
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imx23_powerreg.h 48 #define HW_POWER_CTRL_RSRVD3 __BIT(31)
49 #define HW_POWER_CTRL_CLKGATE __BIT(30)
51 #define HW_POWER_CTRL_PSWITCH_MID_TRAN __BIT(27)
53 #define HW_POWER_CTRL_DCDC4P2_BO_IRQ __BIT(24)
54 #define HW_POWER_CTRL_ENIRQ_DCDC4P2_BO __BIT(23)
55 #define HW_POWER_CTRL_VDD5V_DROOP_IRQ __BIT(22)
56 #define HW_POWER_CTRL_ENIRQ_VDD5V_DROOP __BIT(21)
57 #define HW_POWER_CTRL_PSWITCH_IRQ __BIT(20)
58 #define HW_POWER_CTRL_PSWITCH_IRQ_SRC __BIT(19)
59 #define HW_POWER_CTRL_POLARITY_PSWITCH __BIT(18
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imxcspireg.h 42 #define CSPI_CON_SSPOL __BIT(7) /* SPI SS Polarity Select */
43 #define CSPI_CON_SSCTL __BIT(6) /* In master mode, this bit
47 #define CSPI_CON_PHA __BIT(5) /* PHA */
48 #define CSPI_CON_POL __BIT(4) /* POL */
49 #define CSPI_CON_SMC __BIT(3) /* SMC */
50 #define CSPI_CON_XCH __BIT(2) /* XCH */
51 #define CSPI_CON_MODE __BIT(1) /* MODE */
52 #define CSPI_CON_ENABLE __BIT(0) /* EN */
55 #define CSPI_IMX31_INTR_TC_EN __BIT(8) /* TX Complete */
56 #define CSPI_IMX31_INTR_BO_EN __BIT(7) /* Bit Counter Overflow *
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imx23_sspreg.h 51 #define HW_SSP_CTRL0_SFTRST __BIT(31)
52 #define HW_SSP_CTRL0_CLKGATE __BIT(30)
53 #define HW_SSP_CTRL0_RUN __BIT(29)
54 #define HW_SSP_CTRL0_SDIO_IRQ_CHECK __BIT(28)
55 #define HW_SSP_CTRL0_LOCK_CS __BIT(27)
56 #define HW_SSP_CTRL0_IGNORE_CRC __BIT(26)
57 #define HW_SSP_CTRL0_READ __BIT(25)
58 #define HW_SSP_CTRL0_DATA_XFER __BIT(24)
60 #define HW_SSP_CTRL0_WAIT_FOR_IRQ __BIT(21)
61 #define HW_SSP_CTRL0_WAIT_FOR_CMD __BIT(20
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  /src/sys/net/
if_wg.h 38 #define WG_IOCTL_SET_PRIVATE_KEY __BIT(0)
39 #define WG_IOCTL_SET_LISTEN_PORT __BIT(1)
40 #define WG_IOCTL_ADD_PEER __BIT(2)
41 #define WG_IOCTL_DELETE_PEER __BIT(3)
  /src/sys/arch/arm/xilinx/
zynq_uartreg.h 33 #define CR_STPBRK __BIT(8)
34 #define CR_STTBRK __BIT(7)
35 #define CR_RSTTO __BIT(6)
36 #define CR_TXDIS __BIT(5)
37 #define CR_TXEN __BIT(4)
38 #define CR_RXDIS __BIT(3)
39 #define CR_RXEN __BIT(2)
40 #define CR_TXRES __BIT(1)
41 #define CR_RXRES __BIT(0)
58 #define MR_CLKS __BIT(0
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zynq_usbreg.h 40 #define HWHOST_HC __BIT(0)
43 #define HWDEVICE_DC __BIT(0)
51 #define ULPI_WU __BIT(31)
52 #define ULPI_RUN __BIT(30)
53 #define ULPI_RW __BIT(29)
54 #define ULPI_SS __BIT(27)
61 #define OTGSC_DPIE __BIT(30)
62 #define OTGSC_1MSE __BIT(29)
63 #define OTGSC_BSEIE __BIT(28)
64 #define OTGSC_BSVIE __BIT(27
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  /src/sys/arch/arm/amlogic/
meson_sdioreg.h 45 #define SDIO_SEND_RESPONSE_NO_CRC __BIT(16)
46 #define SDIO_SEND_RESPONSE_DATA __BIT(17)
47 #define SDIO_SEND_RESPONSE_CRC7_FROM_8 __BIT(18)
48 #define SDIO_SEND_CHECK_BUSY_DAT0 __BIT(19)
49 #define SDIO_SEND_COMMAND_HAS_DATA __BIT(20)
50 #define SDIO_SEND_USE_INT_WINDOW __BIT(21)
54 #define SDIO_CONF_COMMAND_DISABLE_CRC __BIT(10)
55 #define SDIO_CONF_COMMAND_OUT_AT_POSEDGE __BIT(11)
57 #define SDIO_CONF_NO_DELAY_DATA __BIT(18)
58 #define SDIO_CONF_DATA_LATCH_AT_NEGEDGE __BIT(19
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meson_rtcreg.h 39 #define AO_RTC_REG0_UNUSED_23 __BIT(23)
40 #define AO_RTC_REG0_SERIAL_BUSY __BIT(22)
41 #define AO_RTC_REG0_UNUSED_21 __BIT(21)
42 #define AO_RTC_REG0_SCLK_STATIC __BIT(20)
44 #define AO_RTC_REG0_SERIAL_START __BIT(17)
45 #define AO_RTC_REG0_ONE_SHOT_POLARITY __BIT(16)
46 #define AO_RTC_REG0_RESERVED_15_11 __BIT(15,11)
48 #define AO_RTC_REG0_RESERVED_7_6 __BIT(7,6)
49 #define AO_RTC_REG0_TEST_MODE __BIT(5)
50 #define AO_RTC_REG0_TEST_CLK __BIT(4
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meson_uart.h 39 #define UART_CONTROL_TX_INT_EN __BIT(28)
40 #define UART_CONTROL_RX_INT_EN __BIT(27)
41 #define UART_CONTROL_CLEAR_ERR __BIT(24)
42 #define UART_CONTROL_RX_RESET __BIT(23)
43 #define UART_CONTROL_TX_RESET __BIT(22)
44 #define UART_CONTROL_RX_EN __BIT(13)
45 #define UART_CONTROL_TX_EN __BIT(12)
47 #define UART_STATUS_RX_BUSY __BIT(26)
48 #define UART_STATUS_TX_BUSY __BIT(25)
49 #define UART_STATUS_TX_EMPTY __BIT(22
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  /src/sys/arch/arm/nvidia/
tegra210_carreg.h 35 #define CAR_RST_SOURCE_WDT_EN __BIT(5)
36 #define CAR_RST_SOURCE_WDT_SEL __BIT(4)
37 #define CAR_RST_SOURCE_WDT_SYS_RST_EN __BIT(2)
38 #define CAR_RST_SOURCE_WDT_COP_RST_EN __BIT(1)
39 #define CAR_RST_SOURCE_WDT_CPU_RST_EN __BIT(0)
49 #define CAR_PLLE_SS_CNTL_SSCINVERT __BIT(15)
50 #define CAR_PLLE_SS_CNTL_SSCCENTER __BIT(14)
51 #define CAR_PLLE_SS_CNTL_SSCPDMBYP __BIT(13)
52 #define CAR_PLLE_SS_CNTL_SSCBYP __BIT(12)
53 #define CAR_PLLE_SS_CNTL_INTERP_RESET __BIT(11
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tegra_hdaudioreg.h 35 #define TEGRA_HDA_IFPS_CONFIG_FPCI_EN __BIT(0)
38 #define TEGRA_HDA_IFPS_INTR_EN __BIT(16)
41 #define TEGRA_HDA_CFG_CMD_DISABLE_INTR __BIT(10)
42 #define TEGRA_HDA_CFG_CMD_ENABLE_SERR __BIT(8)
43 #define TEGRA_HDA_CFG_CMD_BUS_MASTER __BIT(2)
44 #define TEGRA_HDA_CFG_CMD_MEM_SPACE __BIT(1)
45 #define TEGRA_HDA_CFG_CMD_IO_SPACE __BIT(0)
48 #define TEGRA_HDA_CFG_BAR0_START __BIT(6)
tegra_usbreg.h 36 #define TEGRA_EHCI_ICUSB_CTRL_ENB1 __BIT(3)
44 #define TEGRA_EHCI_HOSTPC1_DEVLC_STS __BIT(28)
45 #define TEGRA_EHCI_HOSTPC1_DEVLC_PTW __BIT(27)
50 #define TEGRA_EHCI_HOSTPC1_DEVLC_ALPD __BIT(24)
51 #define TEGRA_EHCI_HOSTPC1_DEVLC_PFSC __BIT(23)
52 #define TEGRA_EHCI_HOSTPC1_DEVLC_PHCD __BIT(22)
56 #define TEGRA_EHCI_HOSTPC1_DEVLC_D_ASUS __BIT(17)
57 #define TEGRA_EHCI_HOSTPC1_DEVLC_D_STL __BIT(16)
67 #define TEGRA_EHCI_SUSP_CTRL_UHSIC_RESET __BIT(14)
68 #define TEGRA_EHCI_SUSP_CTRL_ULPI_PHY_ENB __BIT(13
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tegra_cecreg.h 33 #define CEC_SW_CONTROL_MODE __BIT(31)
34 #define CEC_SW_CONTROL_FILTERED_RX_DATA_PIN __BIT(4)
35 #define CEC_SW_CONTROL_RAW_INPUT_DATA_PIN __BIT(0)
38 #define CEC_HW_CONTROL_TX_RX_MODE __BIT(31)
39 #define CEC_HW_CONTROL_FAST_SIM_MODE __BIT(30)
40 #define CEC_HW_CONTROL_TX_NAK_MODE __BIT(24)
41 #define CEC_HW_CONTROL_RX_NAK_MODE __BIT(16)
42 #define CEC_HW_CONTROL_RX_SNOOP __BIT(15)
46 #define CEC_INPUT_FILTER_MODE __BIT(31)
52 #define CEC_TX_REGISTER_RETRY_FRAME __BIT(17
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  /src/sys/dev/ic/
dwc_mmc_reg.h 72 #define DWC_MMC_GCTRL_USE_INTERNAL_DMAC __BIT(25)
73 #define DWC_MMC_GCTRL_SEND_AUTO_STOP_CCSD __BIT(10)
74 #define DWC_MMC_GCTRL_DMAEN __BIT(5)
75 #define DWC_MMC_GCTRL_INTEN __BIT(4)
76 #define DWC_MMC_GCTRL_DMARESET __BIT(2)
77 #define DWC_MMC_GCTRL_FIFORESET __BIT(1)
78 #define DWC_MMC_GCTRL_SOFTRESET __BIT(0)
83 #define DWC_MMC_CLKENA_LOWPOWERON __BIT(16)
84 #define DWC_MMC_CLKENA_CARDCLKON __BIT(0)
90 #define DWC_MMC_CMD_START __BIT(31
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