| /src/sys/arch/ews4800mips/stand/common/ |
| cons_zs.c | 50 zs_set_addr(uint32_t csr, uint32_t data, int clock)
53 zs.csr = (volatile uint8_t *)csr;
65 *zs.csr = reg; \
66 *zs.csr = val; \
92 *zs.csr = ZSWR0_RESET_STATUS;
93 *zs.csr = ZSWR0_RESET_STATUS;
103 int csr, data; local in function:zs_cngetc
106 csr = *zs.csr;
117 int csr, data; local in function:zs_cnscan
131 int csr; local in function:zs_cnputc
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| intel_csr.c | 37 * DOC: csr support for dmc
39 * Display Context Save and Restore (CSR) firmware support added from gen9
304 * CSR firmware is read from a .bin file and kept in internal memory one time.
310 u32 *payload = dev_priv->csr.dmc_payload;
314 DRM_ERROR("No CSR support available for this platform\n");
318 if (!dev_priv->csr.dmc_payload) {
319 DRM_ERROR("Tried to program CSR with empty payload\n");
323 fw_size = dev_priv->csr.dmc_fw_size;
333 for (i = 0; i < dev_priv->csr.mmio_count; i++) {
334 I915_WRITE(dev_priv->csr.mmioaddr[i]
592 struct intel_csr *csr = &dev_priv->csr; local in function:parse_csr_fw
639 struct intel_csr *csr; local in function:csr_load_work_fn
680 struct intel_csr *csr = &dev_priv->csr; local in function:intel_csr_ucode_init
[all...] |
| /src/sys/dev/ic/ |
| lsi64854.c | 87 uint32_t csr; local in function:lsi64854_attach
113 csr = L64854_GCSR(sc);
114 sc->sc_rev = csr & L64854_DEVID;
139 DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr));
150 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \
206 uint32_t csr; local in function:lsi64854_reset
209 csr = L64854_GCSR(sc);
211 DPRINTF(LDB_ANY, ("%s: csr 0x%x\n", __func__, csr));
286 uint32_t csr; local in function:lsi64854_setup
377 uint32_t csr; local in function:lsi64854_scsi_intr
505 uint32_t csr; local in function:lsi64854_enet_intr
544 uint32_t csr; local in function:lsi64854_setup_pp
614 uint32_t csr; local in function:lsi64854_pp_intr
[all...] |
| mk48txx.c | 110 uint8_t csr; local in function:mk48txx_gettime_ymdhms
115 csr = (*sc->sc_nvrd)(sc, clkoff + MK48TXX_ICSR);
116 csr |= MK48TXX_CSR_READ;
117 (*sc->sc_nvwr)(sc, clkoff + MK48TXX_ICSR, csr);
128 year += 100*bcdtobin(csr & MK48TXX_CSR_CENT_MASK);
139 csr = (*sc->sc_nvrd)(sc, clkoff + MK48TXX_ICSR);
140 csr &= ~MK48TXX_CSR_READ;
141 (*sc->sc_nvwr)(sc, clkoff + MK48TXX_ICSR, csr);
155 uint8_t csr; local in function:mk48txx_settime_ymdhms
173 csr = (*sc->sc_nvrd)(sc, clkoff + MK48TXX_ICSR)
[all...] |
| wd33c93.c | 293 u_char csr, reg; local in function:wd33c93_reset
320 GET_SBIC_csr(sc, csr); /* clears interrupt also */
323 switch (csr) {
882 int csr; local in function:wd33c93_wait
883 GET_SBIC_csr(sc, csr);
884 printf("wd33c93_wait: TIMEO @%d with asr=x%x csr=x%x\n",
885 line, val, csr);
902 u_char csr, asr; local in function:wd33c93_abort
905 GET_SBIC_csr(sc, csr);
908 printf ("ABORT in %s: csr=0x%02x, asr=0x%02x\n", where, csr, asr)
985 u_char target, lun, asr, csr, id; local in function:wd33c93_selectbus
1271 u_char phase, csr; local in function:wd33c93_xferdone
1313 u_char csr, asr; local in function:wd33c93_go
1380 u_char asr, csr; local in function:wd33c93_intr
1423 u_char asr, csr=0; local in function:wd33c93_poll
1475 u_char asr, csr, *msg; local in function:wd33c93_msgin_phase
[all...] |
| /src/sys/arch/pmax/pmax/ |
| dec_3max.c | 130 uint32_t csr; local in function:dec_3max_init
153 csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
154 csr &= ~(KN02_CSR_WRESERVED|KN02_CSR_IOINTEN|KN02_CSR_CORRECT|0xff);
155 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr;
227 uint32_t csr; local in function:dec_3max_intr_establish
239 csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) &
241 csr |= (kn02intrs[i].intrbit << 16);
242 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr;
256 uint32_t csr; local in function:dec_3max_intr
262 csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR)
317 uint32_t erradr, csr; local in function:dec_3max_errintr
[all...] |
| /src/sys/dev/sbus/ |
| cs4231_sbus.c | 231 uint32_t csr; local in function:cs4231_sbus_trigger_output
263 csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR);
265 snprintb(bits, sizeof(bits), APC_BITS, csr);
267 DPRINTF(("trigger_output: csr=%s\n", bits));
268 if ((csr & PDMA_GO) == 0 || (csr & APC_PPAUSE) != 0) {
271 csr &= ~(APC_PPAUSE | APC_PMIE | APC_INTR_MASK);
272 bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR, csr);
274 csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR);
275 csr &= ~APC_INTR_MASK
316 uint32_t csr; local in function:cs4231_sbus_halt_output
363 uint32_t csr; local in function:cs4231_sbus_trigger_input
447 uint32_t csr; local in function:cs4231_sbus_halt_input
493 uint32_t csr; local in function:cs4231_sbus_intr
[all...] |
| if_le_ledma.c | 157 uint32_t csr; local in function:lesetutp
159 csr = L64854_GCSR(dma);
160 csr |= E_TP_AUI;
161 L64854_SCSR(dma, csr);
169 uint32_t csr; local in function:lesetaui
171 csr = L64854_GCSR(dma);
172 csr &= ~E_TP_AUI;
173 L64854_SCSR(dma, csr);
229 uint32_t csr; local in function:lehwreset
235 csr = L64854_GCSR(dma)
[all...] |
| /src/sys/arch/sun3/dev/ |
| dma.c | 156 printf("%s: line %d: CSR = 0x%x\n", \
206 uint32_t csr; local in function:dma_reset
212 csr = DMA_GCSR(sc);
214 csr |= D_RESET; /* reset DMA */
215 DMA_SCSR(sc, csr);
219 csr = DMA_GCSR(sc);
220 csr &= ~D_RESET; /* de-assert reset line */
221 DMA_SCSR(sc, csr);
230 csr = DMA_GCSR(sc);
231 csr |= D_INT_EN; /* enable interrupts *
248 uint32_t csr; local in function:dma_setup
311 uint32_t csr; local in function:espdmaintr
[all...] |
| memerr.c | 68 const char *sc_csrbits; /* how to print csr bits */
162 uint8_t csr, ctx; local in function:memerr_interrupt
167 csr = me->me_csr;
168 if ((csr & ME_CSR_IPEND) == 0)
181 snprintb(bits, sizeof(bits), sc->sc_csrbits, csr);
182 printf(" csr=%s\n", bits);
189 if (csr & ME_PAR_EMASK) {
200 if (csr & (ME_ECC_WBTMO | ME_ECC_WBERR)) {
204 if (csr & ME_ECC_UE) {
208 if (csr & ME_ECC_CE)
[all...] |
| /src/sys/arch/cobalt/stand/boot/ |
| zs.c | 140 uint8_t csr; local in function:zs_putc
143 csr = zs_read(dev, ZS_CSR);
144 } while ((csr & ZSRR0_TX_READY) == 0);
152 uint8_t csr, data; local in function:zs_getc
155 csr = zs_read(dev, ZS_CSR);
156 } while ((csr & ZSRR0_RX_READY) == 0);
165 uint8_t csr, data; local in function:zs_scan
167 csr = zs_read(dev, ZS_CSR);
168 if ((csr & ZSRR0_RX_READY) == 0)
|
| /src/sys/arch/sgimips/stand/common/ |
| iris_scsi.c | 104 uint8_t csr; local in function:wd33c93_reset
127 GET_SBIC_csr(sc, csr);
128 __USE(csr);
165 uint8_t csr, asr; local in function:wd33c93_go
172 if ((csr = wd33c93_selectbus(sc, cbuf, clen, buf, lenp)) == 0)
182 i = wd33c93_nextstate(sc, cbuf, clen, buf, lenp, csr, asr);
191 GET_SBIC_csr(sc, csr);
216 * Returns the current CSR following selection and optionally MSG out phase.
217 * i.e. the returned CSR *should* indicate CMD phase...
224 uint8_t asr, csr, id, lun, target local in function:wd33c93_selectbus
531 uint8_t asr, csr; local in function:wd33c93_intr
614 uint8_t phase, csr; local in function:wd33c93_xferdone
645 uint8_t csr, asr; local in function:wd33c93_abort
723 uint8_t asr, csr = 0; local in function:wd33c93_poll
769 uint8_t asr, csr, *msg; local in function:wd33c93_msgin_phase
[all...] |
| /src/sys/arch/hp300/dev/ |
| hp98265reg.h | 52 #define SCSI_IPL(csr) ((((csr) >> 4) & 3) + 3)
|
| /src/sys/arch/sh3/dev/ |
| adc.c | 75 ADC_(CSR) = 0;
124 uint8_t csr; local in function:adc_sample_channel
141 csr = ADC_(CSR);
142 if ((csr & SH7709_ADCSR_ADST) != 0) {
144 snprintb(bits, sizeof(bits), SH7709_ADCSR_BITS, csr);
145 printf("adc_sample_channel(%d): CSR=%s", chan, bits);
155 ADC_(CSR) = chan | SH7709_ADCSR_ADST | SH7709_ADCSR_CKS;
158 csr = ADC_(CSR);
[all...] |
| /src/sys/dev/vme/ |
| si.c | 364 uint16_t csr; local in function:si_intr
370 csr = SIREG_READ(ncr_sc, SIREG_CSR);
372 NCR_TRACE("si_intr: csr=0x%x\n", csr);
374 if (csr & SI_CSR_DMA_CONFLICT) {
378 if (csr & SI_CSR_DMA_BUS_ERR) {
386 csr |= SI_CSR_DMA_IP;
389 if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) {
420 * The reset bits in the CSR are active low.
561 int tmo, csr_mask, csr; local in function:si_dma_poll
608 uint16_t csr; local in function:si_intr_on
630 uint16_t csr; local in function:si_intr_off
655 uint16_t csr; local in function:si_dma_setup
729 uint16_t csr; local in function:si_dma_start
796 uint16_t csr; local in function:si_dma_stop
[all...] |
| /src/sys/arch/amiga/dev/ |
| sbic.c | 188 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \
199 u_char csr; member in struct:__anona8e794960108
214 sbic_trace[sbic_traceptr].csr = csr_traceptr; \
227 int csr; member in struct:__anona8e794960208
701 int csr; local in function:sbicwait
710 GET_SBIC_csr(regs, csr);
711 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n",
712 line, val, csr);
729 u_char csr, asr; local in function:sbicabort
732 GET_SBIC_csr(regs, csr);
855 u_char csr; local in function:sbicreset
968 u_char asr, csr, id; local in function:sbicselectbus
1234 u_char orig_csr, csr, asr; local in function:sbicxfin
1318 u_char phase, csr, asr; local in function:sbicicmd
1561 u_char phase, asr, csr; local in function:sbicxfdone
1606 u_char csr, asr, *addr; local in function:sbicgo
1821 u_char asr, csr; local in function:sbicintr
1868 u_char asr, csr; local in function:sbicpoll
1929 u_char asr, csr, *tmpaddr; local in function:sbicmsgin
2621 u_char csr, asr; local in function:sbicdumpstate
2688 u_char csr, asr; local in function:sbic_dump
[all...] |
| /src/sys/arch/arm/marvell/ |
| mvsocpmu.c | 101 uint32_t csr; local in function:mvsocpmu_tm_init
104 csr = MVSOCPMU_TM_READ(sc, CSR);
105 sc->sc_deflims.sel_warnmin = UC2UK(sc->sc_val2uc(TM_CSR_COOLTHR(csr)));
107 UC2UK(sc->sc_val2uc(TM_CSR_OVERHEATTHR(csr)));
140 uint32_t csr, uc, uk; local in function:mvsocpmu_tm_refresh
142 csr = MVSOCPMU_TM_READ(sc, CSR);
143 if (csr & TM_CSR_TMDIS) {
147 uc = sc->sc_val2uc(TM_CSR_THERMTEMPOUT(csr)); /* uC *
158 uint32_t csr; local in function:mvsocpmu_tm_get_limits
171 uint32_t csr, mask; local in function:mvsocpmu_tm_set_limits
[all...] |
| /src/sys/arch/acorn32/podulebus/ |
| sbic.c | 100 * The UPROTECTED_CSR code is bogus. It can read the csr (SCSI Status
212 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \
221 u_char csr; member in struct:__anonbe1231a30108
236 sbic_trace[sbic_traceptr].csr = csr_traceptr; \
246 int csr; member in struct:__anonbe1231a30208
612 int csr; local in function:sbicwait
621 GET_SBIC_csr(regs, csr);
622 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n",
623 line, val, csr);
640 u_char csr, asr local in function:sbicabort
785 u_char csr; local in function:sbicreset
903 u_char asr, csr, id; local in function:sbicselectbus
1174 u_char orig_csr, csr; local in function:sbicxfin
1251 u_char phase, csr, asr; local in function:sbicicmd
1488 u_char phase, asr, csr; local in function:sbicxfdone
1535 u_char asr = 0, csr = 0; local in function:sbicgo
1649 u_char asr, csr; local in function:sbicintr
1700 u_char asr, csr; local in function:sbicpoll
1764 u_char asr, csr, *tmpaddr; local in function:sbicmsgin
2360 u_char csr, asr; local in function:sbicdumpstate
2425 u_char csr, asr; local in function:sbic_dump
[all...] |
| /src/sys/arch/sparc/dev/ |
| sw.c | 398 u_short csr; local in function:sw_intr
404 csr = SWREG_READ(ncr_sc, SWREG_CSR);
406 NCR_TRACE("sw_intr: csr=0x%x\n", csr);
408 if (csr & SW_CSR_DMA_CONFLICT) {
412 if (csr & SW_CSR_DMA_BUS_ERR) {
420 csr |= SW_CSR_DMA_IP;
423 if (csr & (SW_CSR_SBC_IP | SW_CSR_DMA_IP)) {
450 * The reset bits in the CSR are active low.
589 int tmo, csr_mask, csr; local in function:sw_dma_poll
633 uint32_t csr; local in function:sw_intr_on
650 uint32_t csr; local in function:sw_intr_off
670 uint32_t csr; local in function:sw_dma_setup
693 uint32_t csr; local in function:sw_dma_start
826 uint32_t csr; local in function:sw_dma_stop
[all...] |
| /src/sys/arch/atari/pci/ |
| pci_machdep.c | 97 uint32_t csr; member in struct:pci_memreg
229 pcireg_t csr; local in function:init_pci_bus
245 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
246 csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
247 csr &= ~PCI_COMMAND_MASTER_ENABLE;
248 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
290 if ((q != self) && (q->csr & what)) {
333 pcireg_t csr, address, mask; local in function:enable_pci_devices
338 csr = 0;
355 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)
[all...] |
| pci_milan.c | 172 uint32_t csr; local in function:milan_vga_init
177 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
178 csr |= (PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
179 csr |= PCI_COMMAND_MASTER_ENABLE;
180 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
|
| /src/sys/arch/mvme68k/dev/ |
| sbic.c | 729 int csr; local in function:sbicwait
730 GET_SBIC_csr(regs, csr);
731 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n",
732 line, val, csr);
751 u_char csr, asr; local in function:sbicabort
754 GET_SBIC_csr(regs, csr);
756 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n",
757 device_xname(dev->sc_dev), where, csr, asr);
806 GET_SBIC_csr (regs, csr);
807 QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr))
880 u_char csr; local in function:sbicreset
956 u_char target = dev->target, lun = dev->lun, asr, csr, id; local in function:sbicselectbus
1299 u_char csr, asr; local in function:sbicicmd
1489 u_char phase, csr; local in function:sbicxfdone
1535 u_char csr, asr, *addr; local in function:sbicgo
1662 u_char asr, csr; local in function:sbicintr
1708 u_char asr, csr = SBIC_CSR_RESET; \/* XXX: Quell un-init warning *\/ local in function:sbicpoll
1777 u_char asr, csr, *tmpaddr, *msgaddr; local in function:sbicmsgin
[all...] |
| /src/sys/arch/vax/vsa/ |
| tc_vsbus.c | 143 uint32_t *csr; local in function:tc_vsbus_match
181 csr = (uint32_t *)va->va_addr;
182 *csr |= KA4x_TCA_CSR_TC_TMO;
184 *csr &= ~KA4x_TCA_CSR_TC_TMO;
202 uint32_t csr; local in function:tc_vsbus_attach
209 aprint_normal(": failed to map TCA CSR: %d\n", error);
216 csr = bus_space_read_4(bst, bsh_csr, 0);
217 csr &= ~(KA4x_TCA_CSR_TC_TMO | KA4x_TCA_CSR_RST_TC);
218 csr |= KA4x_TCA_CSR_ERR | KA4x_TCA_CSR_INVAL_REF;
219 bus_space_write_4(bst, bsh_csr, 0, csr);
344 uint32_t csr; local in function:tc_vsbus_intr
[all...] |
| /src/sys/arch/next68k/next68k/ |
| clock.c | 68 timer->csr |= TIMER_REG_UPDATE;
100 timer->csr = 0;
103 timer->csr = TIMER_REG_ENABLE|TIMER_REG_UPDATE;
|
| /src/sys/dev/ebus/ |
| cs4231_ebus.c | 288 u_int32_t csr; local in function:cs4231_ebus_dma_reset
295 csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
296 if ((csr & (EBDMA_CYC_PEND | EBDMA_DRAIN)) == 0)
302 snprintb(bits, sizeof(bits), EBUS_DCSR_BITS, csr);
303 printf("cs4231_ebus_dma_reset: timed out: csr=%s\n", bits);
307 bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr & ~EBDMA_RESET);
343 uint32_t csr; local in function:cs4231_ebus_trigger_transfer
357 csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
359 csr | EBDMA_EN_NEXT | (iswrite ? EBDMA_WRITE : 0)
437 u_int32_t csr; local in function:cs4231_ebus_halt_output
461 uint32_t csr; local in function:cs4231_ebus_halt_input
484 uint32_t csr; local in function:cs4231_ebus_dma_intr
[all...] |
