| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| selftest_rc6.c | 116 struct intel_engine_cs *engine, **engines; local in function:randomised_engines
126 engines = kmalloc_array(n, sizeof(*engines), GFP_KERNEL);
127 if (!engines)
132 engines[n++] = engine;
134 i915_prandom_shuffle(engines, sizeof(*engines), n, prng);
137 return engines;
143 struct intel_engine_cs **engines; local in function:live_rc6_ctx_wa
152 engines = randomised_engines(gt, &prng, &count)
[all...] |
| debugfs_engines.c | 32 DEFINE_GT_DEBUGFS_ATTRIBUTE(engines);
37 { "engines", &engines_fops },
|
| intel_engine_user.c | 133 struct list_head *engines)
140 list_add(&engine->uabi_node.list, engines);
142 list_sort(NULL, engines, engine_cmp);
162 for_each_uabi_engine(engine, i915) { /* all engines must agree! */
246 LIST_HEAD(engines);
248 sort_engines(i915, &engines);
258 list_for_each_safe(it, next, &engines) {
264 continue; /* ignore incomplete engines */
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gem/ |
| i915_gem_context.h | 175 return rcu_dereference_protected(ctx->engines,
200 struct i915_gem_engines *e = rcu_dereference(ctx->engines);
201 if (likely(idx < e->num_engines && e->engines[idx]))
202 ce = intel_context_get(e->engines[idx]);
210 struct i915_gem_engines *engines)
212 GEM_BUG_ON(!engines);
213 it->engines = engines;
220 #define for_each_gem_engine(ce, engines, it) \
221 for (i915_gem_engines_iter_init(&(it), (engines)); \
[all...] |
| i915_gem_context_types.h | 37 struct intel_context *engines[]; member in struct:i915_gem_engines
42 const struct i915_gem_engines *engines; member in struct:i915_gem_engines_iter
59 * @engines: User defined engines for this context
66 * engines.
79 struct i915_gem_engines __rcu *engines; member in struct:i915_gem_context
80 struct mutex engines_mutex; /* guards writes to engines */
|
| i915_gem_context.c | 254 if (!e->engines[count])
257 RCU_INIT_POINTER(e->engines[count]->gem_context, NULL);
258 intel_context_put(e->engines[count]);
280 e = kzalloc(struct_size(e, engines, I915_NUM_ENGINES), GFP_KERNEL);
292 GEM_BUG_ON(e->engines[engine->legacy_idx]);
302 e->engines[engine->legacy_idx] = ce;
318 free_engines(rcu_access_pointer(ctx->engines));
366 return rcu_dereference_protected(ctx->engines, true);
472 * Map the user's engine back to the actual engines; one virtual
473 * engine will be mapped to multiple engines, and using ctx->engine[
1482 struct i915_gem_engines *engines; member in struct:set_engines
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/fifo/ |
| chan.h | 27 u64 engines, int bar, u32 base, u32 user,
|
| nouveau_nvkm_engine_fifo_chan.c | 213 u64 mask = chan->engines;
418 u64 hvmm, u64 push, u64 engines, int bar, u32 base,
431 chan->engines = engines;
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvif/ |
| nouveau_nvif_fifo.c | 67 device->runlist[i].engines = a->v.runlist[i].data;
98 if (device->runlist[i].engines & a.v.engine.data)
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gem/selftests/ |
| mock_context.c | 37 RCU_INIT_POINTER(ctx->engines, e);
|
| huge_pages.c | 1118 struct i915_gem_engines *engines; local in function:igt_write_huge
1154 * To keep things interesting when alternating between engines in our
1171 engines = i915_gem_context_lock_engines(ctx);
1178 ce = engines->engines[order[i] % engines->num_engines];
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/engine/ |
| fifo.h | 22 u64 engines; member in struct:nvkm_fifo_chan
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvif/ |
| device.h | 16 u64 engines; member in struct:nvif_device::nvif_fifo_runlist
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/marvell/ |
| armada-80x0.dtsi | 104 * to enable two cryptographic engines in
|
| /src/sys/external/bsd/drm2/dist/drm/i915/selftests/ |
| intel_memory_region.c | 309 struct i915_gem_engines *engines; local in function:igt_gpu_write
352 engines = i915_gem_context_lock_engines(ctx);
357 ce = engines->engines[order[i] % engines->num_engines];
|
| /src/sys/external/bsd/drm2/dist/include/uapi/drm/ |
| i915_drm.h | 114 * Different engines serve different roles, and there may be more than one
117 * operations to be performed on a certain subset of engines, or for providing
577 * value reports the support of context isolation for individual engines by
1005 * clients or engines (i.e. suballocating objects), the implicit tracking
1230 * conditions which prevent the report of which engines are busy from
1232 * object is idle, the result of the ioctl, that all engines are idle,
1245 * The high word (bits 16:31) are a bitmask of which engines classes
1246 * are currently reading from the object. Multiple engines may be
1253 * execution engines, e.g. multiple media engines, which ar
1713 struct i915_engine_class_instance engines[0]; member in struct:i915_context_engines_load_balance
1751 struct i915_engine_class_instance engines[0]; member in struct:i915_context_engines_bond
1768 struct i915_engine_class_instance engines[0]; member in struct:i915_context_param_engines
2229 struct drm_i915_engine_info engines[]; member in struct:drm_i915_query_engine_info
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| amdgpu_dce80_resource.c | 807 if (pool->base.engines[i] != NULL)
808 dce110_engine_destroy(&pool->base.engines[i]);
1061 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1062 if (pool->base.engines[i] == NULL) {
1258 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1259 if (pool->base.engines[i] == NULL) {
1451 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1452 if (pool->base.engines[i] == NULL) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_aux.c | 446 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
568 aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| amdgpu_dce100_resource.c | 759 if (pool->base.engines[i] != NULL)
760 dce110_engine_destroy(&pool->base.engines[i]);
1099 pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
1100 if (pool->base.engines[i] == NULL) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_resource.c | 625 if (pool->base.engines[i] != NULL)
626 dce110_engine_destroy(&pool->base.engines[i]);
1196 pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
1197 if (pool->base.engines[i] == NULL) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 172 struct dce_aux *engines[MAX_PIPES]; member in struct:resource_pool
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_link_ddc.c | 664 if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout)
666 ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_resource.c | 816 if (pool->base.engines[i] != NULL)
817 dce110_engine_destroy(&pool->base.engines[i]);
1457 pool->base.engines[i] = dce110_aux_engine_create(ctx, i);
1458 if (pool->base.engines[i] == NULL) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_resource.c | 777 if (pool->base.engines[i] != NULL)
778 dce110_engine_destroy(&pool->base.engines[i]);
1343 pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
1344 if (pool->base.engines[i] == NULL) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_resource.c | 976 if (pool->base.engines[i] != NULL)
977 dce110_engine_destroy(&pool->base.engines[i]);
1544 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
1545 if (pool->base.engines[i] == NULL) {
|
