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  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_gart.c 44 * GART
45 * The GART (Graphics Aperture Remapping Table) is an aperture
51 * Radeon GPUs support both an internal GART, as described above,
52 * and AGP. AGP works similarly, but the GART table is configured
57 * Both AGP and internal GART can be used at the same time, however
60 * This file handles the common internal GART management.
64 * Common GART table functions.
67 * radeon_gart_table_ram_alloc - allocate system ram for gart page table
71 * Allocate system memory for GART page table
73 * gart table to be in system memory
    [all...]
radeon_rs400.c 50 /* Check gart size */
61 DRM_ERROR("Unable to use IGP GART size %uM\n",
63 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
64 DRM_ERROR("Forcing to 32M GART size\n");
90 if (rdev->gart.ptr) {
91 WARN(1, "RS400 GART already initialized\n");
94 /* Check gart size */
107 /* Initialize common gart structure */
112 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
113 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4
    [all...]
radeon_asic.c 157 * Removes AGP flags and changes the gart callbacks on AGP
158 * cards when using the internal gart rather than AGP (all asics).
172 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
173 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
174 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
178 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
179 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
180 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
214 .gart = {
282 .gart =
    [all...]
radeon_rs600.c 36 * R4XX family. The GART is different from the RS400 one and is very
38 * of the RS600 GART block).
524 * GART.
548 if (rdev->gart.robj) {
549 WARN(1, "RS600 GART already initialized\n");
552 /* Initialize common gart structure */
557 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
566 if (rdev->gart.robj == NULL) {
567 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n")
    [all...]
radeon_r300.c 89 * rv370,rv380 PCIE GART
147 void __iomem *ptr = rdev->gart.ptr;
164 if (rdev->gart.robj) {
165 WARN(1, "RV370 PCIE GART already initialized\n");
168 /* Initialize common gart structure */
174 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
175 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
176 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
177 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry
    [all...]
radeon_r100.c 636 * PCI GART
642 * entry otherwise if first GPU GART read hit this entry it
650 if (rdev->gart.ptr) {
651 WARN(1, "R100 PCI GART already initialized\n");
654 /* Initialize common gart structure */
658 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
659 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
660 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
661 rdev->asic->gart.set_page = &r100_pci_gart_set_page
    [all...]
radeon_ttm.c 1258 if (p >= rdev->gart.num_cpu_pages)
1261 page = rdev->gart.pages[p];
1267 kunmap(rdev->gart.pages[p]);
radeon_vm.c 42 * GPUVM is similar to the legacy gart on older asics, however
43 * rather than there being a single global gart table
375 uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8;
593 * radeon_vm_map_gart - get the physical address of a gart page
607 result = rdev->gart.pages_entry[addr >> RADEON_GPU_PAGE_SHIFT];
radeon_ni.c 1270 * GART
1285 if (rdev->gart.robj == NULL) {
1286 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1314 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1358 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1360 (unsigned long long)rdev->gart.table_addr);
1361 rdev->gart.ready = true;
1417 /* flush read cache over gart for this vmid */
1460 /* flush read cache over gart for this vmid */
radeon_rv770.c 900 * GART
907 if (rdev->gart.robj == NULL) {
908 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
936 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
945 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
947 (unsigned long long)rdev->gart.table_addr);
948 rdev->gart.ready = true;
radeon_r600.c 1101 * R600 PCIE GART
1111 void __iomem *ptr = rdev->gart.ptr;
1150 if (rdev->gart.robj) {
1151 WARN(1, "R600 PCIE GART already initialized\n");
1154 /* Initialize common gart structure */
1158 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
1167 if (rdev->gart.robj == NULL) {
1168 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1204 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gart.c 44 * GART
45 * The GART (Graphics Aperture Remapping Table) is an aperture
51 * Radeon GPUs support both an internal GART, as described above,
52 * and AGP. AGP works similarly, but the GART table is configured
57 * Both AGP and internal GART can be used at the same time, however
60 * This file handles the common internal GART management.
64 * Common GART table functions.
73 * This dummy page is used by the driver as a filler for gart entries
74 * when pages are taken out of the GART
164 * amdgpu_gart_table_vram_alloc - allocate vram for gart page tabl
    [all...]
amdgpu_gmc_v10_0.c 259 * GART
272 /* Use register 17 for GART */
334 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
381 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
679 * vram and gart within the GPU's physical address space.
702 /* set the gart size */
724 if (adev->gart.bo) {
725 WARN(1, "NAVI10 PCIE GART already initialized\n");
729 /* Initialize common gart structure */
734 adev->gart.table_size = adev->gart.num_gpu_pages * 8
    [all...]
amdgpu_gmc_v6_0.c 351 /* set the gart size */
494 if (adev->gart.bo == NULL) {
495 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
502 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
577 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
580 adev->gart.ready = true;
588 if (adev->gart.bo) {
589 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
595 adev->gart.table_size = adev->gart.num_gpu_pages * 8
    [all...]
amdgpu_gmc_v7_0.c 262 * Set the location of vram, gart, and AGP in the GPU's
324 * vram and gart within the GPU's physical address space (CIK).
405 /* set the gart size */
464 * GART
471 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback
612 * gmc_v7_0_gart_enable - gart enable
628 if (adev->gart.bo == NULL) {
629 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
636 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
721 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n"
    [all...]
amdgpu_gmc_v9_0.c 464 * GART
864 * this overrides GART which by default gets placed in first 8M and
956 * vram and gart within the GPU's physical address space.
991 /* set the gart size */
1019 if (adev->gart.bo) {
1020 WARN(1, "VEGA10 PCIE GART already initialized\n");
1023 /* Initialize common gart structure */
1027 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1028 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC)
    [all...]
amdgpu_gtt_mgr.c 209 lpfn = adev->gart.num_cpu_pages;
amdgpu_gmc_v8_0.c 453 * Set the location of vram, gart, and AGP in the GPU's
526 * vram and gart within the GPU's physical address space (VI).
606 /* set the gart size */
666 * GART
673 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
833 * gmc_v8_0_gart_enable - gart enable
849 if (adev->gart.bo == NULL) {
850 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
857 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
959 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n"
    [all...]
amdgpu_ttm.c 1144 /* bind pages into GART page tables */
1156 * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1177 /* allocate GART space */
1593 flags |= adev->gart.gart_pte_flags;
2206 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
2270 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2545 if (p >= adev->gart.num_cpu_pages)
2548 page = adev->gart.pages[p];
2554 kunmap(adev->gart.pages[p]);
amdgpu_gfxhub_v1_0.c 59 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
289 /* GART Enable. */
329 * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
amdgpu_gfxhub_v2_0.c 70 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
276 /* GART Enable. */
312 * gfxhub_v2_0_set_fault_enable_default - update GART/VM fault handling
amdgpu_mmhub_v2_0.c 55 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
267 /* GART Enable. */
305 * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling
  /src/sys/external/bsd/drm2/dist/drm/nouveau/
nouveau_chan.h 20 struct nvif_object gart; member in struct:nouveau_channel
nouveau_chan.c 111 nvif_object_fini(&chan->gart);
362 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
384 /* allocate dma objects to cover all allowed vram, and gart */
422 ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY,
423 &args, sizeof(args), &chan->gart);
  /src/sys/external/bsd/drm/dist/shared-core/
xgi_drm.h 50 * Size of PCI-e GART range in megabytes.
52 struct drm_map gart; member in struct:xgi_bootstrap

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