| /src/sys/arch/arm/footbridge/isa/ |
| icu.h | 53 outb(IO_ICU1 + 1, imen); \
54 outb(IO_ICU2 + 1, imen >> 8); \
|
| isa_machdep.c | 125 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
126 outb(IO_ICU1+1, ICU_OFFSET); /* starting at this vector index */
127 outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */
129 outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */
131 outb(IO_ICU1+1, 1); /* 8086 mode */
133 outb(IO_ICU1+1, 0xff); /* leave interrupts masked */
134 outb(IO_ICU1, 0x68); /* special mask mode (if available) */
135 outb(IO_ICU1, 0x0a); /* Read IRR by default. */
137 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
140 outb(IO_ICU2, 0x11); /* reset; program device, four bytes *
[all...] |
| /src/sys/arch/shark/isa/ |
| icu.h | 53 outb(IO_ICU1 + 1, imen); \
54 outb(IO_ICU2 + 1, imen >> 8); \
|
| isa_shark_machdep.c | 124 outb(IO_ICU1, 0x19); /* reset; four bytes, level triggered */
125 outb(IO_ICU1+1, ICU_OFFSET); /* int base: not used */
126 outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */
127 outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */
128 outb(IO_ICU1+1, 0xff); /* disable all interrupts */
129 outb(IO_ICU1, 0x68); /* special mask mode (if available) */
130 outb(IO_ICU1, 0x0a); /* Read IRR, not ISR */
132 outb(IO_ICU2, 0x19); /* reset; four bytes, level triggered */
133 outb(IO_ICU2+1, ICU_OFFSET+8); /* int base + offset for master: not used */
134 outb(IO_ICU2+1, IRQ_SLAVE); /* who ami i? *
[all...] |
| clock.c | 200 outb(IO_RTC, reg);
208 outb(IO_RTC, reg);
209 outb(IO_RTC+1, datum);
284 outb(IO_TIMER1 + TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT);
285 outb(IO_TIMER1 + TIMER_CNTR0, TIMER0_ROLLOVER % 256);
286 outb(IO_TIMER1 + TIMER_CNTR0, TIMER0_ROLLOVER / 256);
392 outb(IO_TIMER1 + TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
485 outb(IO_TIMER1 + TIMER_MODE,
487 outb(IO_TIMER1 + TIMER_CNTR0, 0xff);
488 outb(IO_TIMER1 + TIMER_CNTR0, 0xff)
[all...] |
| /src/sys/arch/i386/stand/efiboot/ |
| eficpufunc.h | 38 void outb(uint32_t, uint8_t);
|
| eficpufunc.c | 44 outb(uint32_t addr, uint8_t c) function in typeref:typename:void
47 __asm volatile ("outb %%al, %%dx" : : "a"(c), "d"(addr));
|
| /src/sys/arch/x86/x86/ |
| i8259.c | 133 outb(IO_ICU1 + PIC_ICW1, ICW1_SELECT | ICW1_LTIM | ICW1_IC4);
137 outb(IO_ICU1 + PIC_ICW1, ICW1_SELECT | ICW1_IC4);
140 outb(IO_ICU1 + PIC_ICW2, ICU_OFFSET);
142 outb(IO_ICU1 + PIC_ICW3, ICW3_CASCADE(IRQ_SLAVE));
146 outb(IO_ICU1 + PIC_ICW4, ICW4_AEOI | ICW4_8086);
149 outb(IO_ICU1 + PIC_ICW4, ICW4_8086);
152 outb(IO_ICU1 + PIC_OCW1, 0xff);
154 outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM);
156 outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_RR);
159 outb(IO_ICU1 + PIC_OCW2, OCW2_SELECT | OCW2_R | OCW2_SL
[all...] |
| /src/sys/arch/prep/stand/boot/ |
| vreset.c | 167 outb(VGA_GR_PORT, 0x06);
188 outb(VGA_GR_PORT, 0x0b); /* disable linear addressing */
189 outb(VGA_GR_DATA, inb(VGA_GR_DATA) & ~0x30);
191 outb(VGA_GR_PORT, 0x0e); /* disable 256 color mode */
192 outb(VGA_GR_DATA, inb(VGA_GR_DATA) & ~0x01);
193 outb(0xd00, 0xff); /* enable auto-centering */
195 outb(VGA_CR_PORT, 0x33);
196 outb(VGA_CR_DATA, inb(VGA_CR_DATA) & ~0x90);
197 outb(VGA_CR_PORT, 0x32);
198 outb(VGA_CR_DATA, inb(VGA_CR_DATA) | 0x04)
[all...] |
| /src/sys/arch/x86/include/ |
| pio.h | 43 void outb(unsigned, uint8_t);
|
| i8259.h | 50 #define SET_ICUS() (outb(IO_ICU1 + 1, imen), outb(IO_ICU2 + 1, imen >> 8))
92 outb %al,$IO_ICU1
96 outb %al,$ICUADDR
103 outb %al,$IO_ICU1
111 outb %al,$IO_ICU2 /* do the second ICU first */ ;\
113 outb %al,$IO_ICU1
131 outb %al,$(ICUADDR+1)
137 outb %al,$(ICUADDR+1)
|
| /src/sys/arch/rs6000/stand/boot/ |
| io.c | 32 outb(int port, char val) function in typeref:typename:void
41 outb(port, val>>8);
42 outb(port+1, val);
|
| boot.h | 41 void outb(int, char);
|
| /src/sys/arch/i386/stand/lib/ |
| gatea20.c | 61 outb(0x92, data | 0x2);
68 outb(K_CMD, KC_CMD_WOUT);
72 outb(K_RDWR, x_20);
|
| comio_direct.c | 164 outb(combase + com_data, c);
188 outb(combase + com_cfcr, LCR_DLAB);
203 outb(combase + com_dlbl, rate);
204 outb(combase + com_dlbh, rate >> 8);
205 outb(combase + com_cfcr, LCR_8BITS);
206 outb(combase + com_mcr, MCR_DTR | MCR_RTS);
207 outb(combase + com_fifo,
209 outb(combase + com_ier, 0);
|
| cpufunc.h | 44 void outb(unsigned, uint8_t);
|
| /src/sys/arch/arm/include/ |
| pio.h | 44 #define outb(port, byte) bus_space_write_1(&isa_io_bs_tag, (bus_space_handle_t)isa_io_bs_tag.bs_cookie, (port), (byte)) macro
|
| /src/sys/arch/x68k/stand/boot/ |
| ne.h | 30 #define outb(x, b) *(volatile uint8_t *)(x) = (b) macro
|
| /src/sys/arch/bebox/stand/boot/ |
| vreset.c | 450 outb(0x3CE, 0x06);
484 outb(0x3c2, 0x63); /* MISC */
485 outb(0x3c2, 0x67); /* MISC */
498 outb(0x3c2, 0x63); /* MISC */
515 outb(0x3c2, 0x63); /* MISC */
553 outb(0x3c0, (index & 0x1F) | 0x20);
555 outb(0x3c0, (index & 0x1F));
556 outb(0x3c0, data);
568 outb(svp->io_port, svp->io_index);
569 outb(svp->io_port+1, svp->io_value)
[all...] |
| fd.c | 364 outb(FDC_RATE(ctlr), un->un_type->rate); /* rate set */
409 outb(FDC_DATA(ctlr), cmd);
459 outb(FDC_DOR(ctlr), DOR_RESET | DOR_DMAEN | unit
468 outb(FDC_DOR(ctlr), DOR_RESET); /* reset & motor off */
477 outb(FDC_DOR(ctlr), 0); /* fdc reset */
479 outb(FDC_DOR(ctlr), DOR_RESET);
656 outb(INT_CTL0, ICW1_AT); /* ICW1 */
657 outb(INT_CTL1, 0); /* ICW2 for master */
658 outb(INT_CTL1, (1 << CASCADE_IRQ)); /* ICW3 tells slaves */
659 outb(INT_CTL1, ICW4_AT); /* ICW4 *
[all...] |
| io.c | 45 outb(int port, u_char val) function in typeref:typename:void
55 outb(port, val >> 8);
56 outb(port + 1, val);
|
| vga.c | 103 outb(addr_6845, 14);
104 outb(addr_6845+1, pos >> 8);
105 outb(addr_6845, 15);
106 outb(addr_6845+1, pos);
267 outb(addr_6845, 10);
268 outb(addr_6845+1, d->cx);
269 outb(addr_6845, 11);
270 outb(addr_6845+1, 13);
408 outb(0x3C4, 0x01);
409 outb(0x3C5, inb(0x3C5) & ~0x20)
[all...] |
| /src/sys/arch/mac68k/include/ |
| pio.h | 34 #define outb(x, y) \ macro
35 { __asm volatile("outb %0, %1" : : "a" ((unsigned char)(y)) , "d" ((unsigned short)(x))); }
|
| /src/sys/arch/shark/shark/ |
| hat.c | 101 outb(ATSR_REG1_REG,
151 outb(ATSR_REG1_REG,
227 outb(TIMER_MODE, TIMER_SEL2|TIMER_RATEGEN|TIMER_16BIT);
228 outb(TIMER_CNTR2, count % 256);
229 outb(TIMER_CNTR2, count / 256);
|
| /src/sys/arch/i386/mca/ |
| mca_machdep.c | 166 outb(MCA_MB_SETUP_REG, 0xff); /* ensure m/board setup is disabled */
167 outb(MCA_ADAP_SETUP_REG, slot | MCA_ADAP_SET);
169 outb(MCA_ADAP_SETUP_REG, 0);
182 outb(MCA_MB_SETUP_REG, 0xff); /* ensure m/board setup is disabled */
183 outb(MCA_ADAP_SETUP_REG, slot | MCA_ADAP_SET);
184 outb(MCA_POS_REG(reg), data);
185 outb(MCA_ADAP_SETUP_REG, 0);
239 outb(MCA_MB_SETUP_REG, 0xff);
243 outb(MCA_ADAP_SETUP_REG, slot | MCA_ADAP_SET);
255 outb(MCA_ADAP_SETUP_REG, 0)
[all...] |
