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    Searched refs:sc_iwin (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/arch/evbarm/hdl_g/
i80321_mainbus.c 159 sc->sc_iwin[0].iwin_base_lo = VERDE_PMMR_BASE;
160 sc->sc_iwin[0].iwin_base_hi = 0;
161 sc->sc_iwin[0].iwin_xlate = VERDE_PMMR_BASE;
162 sc->sc_iwin[0].iwin_size = VERDE_PMMR_SIZE;
167 sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE |
170 sc->sc_iwin[1].iwin_base_hi = 0;
172 sc->sc_iwin[1].iwin_base_lo = 0;
173 sc->sc_iwin[1].iwin_base_hi = 0;
175 sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE;
176 sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE
    [all...]
  /src/sys/arch/evbarm/iq80321/
i80321_mainbus.c 176 sc->sc_iwin[0].iwin_base_lo = VERDE_PMMR_BASE;
177 sc->sc_iwin[0].iwin_base_hi = 0;
178 sc->sc_iwin[0].iwin_xlate = VERDE_PMMR_BASE;
179 sc->sc_iwin[0].iwin_size = VERDE_PMMR_SIZE;
184 sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE |
187 sc->sc_iwin[1].iwin_base_hi = 0;
189 sc->sc_iwin[1].iwin_base_lo = 0;
190 sc->sc_iwin[1].iwin_base_hi = 0;
192 sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE;
193 sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE
    [all...]
  /src/sys/arch/evbarm/iyonix/
i80321_mainbus.c 176 sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE |
179 sc->sc_iwin[1].iwin_base_hi = 0;
181 sc->sc_iwin[1].iwin_base_lo = 0;
182 sc->sc_iwin[1].iwin_base_hi = 0;
184 sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE;
185 sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE;
188 sc->sc_iwin[2].iwin_base_lo = memstart |
191 sc->sc_iwin[2].iwin_base_hi = 0;
193 sc->sc_iwin[2].iwin_base_lo = 0;
194 sc->sc_iwin[2].iwin_base_hi = 0
    [all...]
  /src/sys/arch/iyonix/iyonix/
i80321_mainbus.c 176 sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE |
179 sc->sc_iwin[1].iwin_base_hi = 0;
181 sc->sc_iwin[1].iwin_base_lo = 0;
182 sc->sc_iwin[1].iwin_base_hi = 0;
184 sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE;
185 sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE;
188 sc->sc_iwin[2].iwin_base_lo = memstart |
191 sc->sc_iwin[2].iwin_base_hi = 0;
193 sc->sc_iwin[2].iwin_base_lo = 0;
194 sc->sc_iwin[2].iwin_base_hi = 0
    [all...]
  /src/sys/arch/evbarm/adi_brh/
becc_mainbus.c 127 sc->sc_iwin[0].iwin_base = physical_start + 128 * 1024 * 1024;
128 sc->sc_iwin[0].iwin_xlate = physical_start;
129 sc->sc_iwin[1].iwin_base = sc->sc_iwin[0].iwin_base+BECC_PCI_MEM1_SIZE;
130 sc->sc_iwin[1].iwin_xlate = physical_start + BECC_PCI_MEM1_SIZE;
131 sc->sc_iwin[2].iwin_base = physical_start;
132 sc->sc_iwin[2].iwin_xlate = physical_start;
  /src/sys/arch/arm/xscale/
i80321.c 121 (0xffffffff - (sc->sc_iwin[0].iwin_size - 1)) & 0xffffffc0);
123 sc->sc_iwin[0].iwin_xlate);
126 PCI_MAPREG_START, sc->sc_iwin[0].iwin_base_lo);
128 PCI_MAPREG_START + 0x04, sc->sc_iwin[0].iwin_base_hi);
130 sc->sc_iwin[0].iwin_base_lo = bus_space_read_4(sc->sc_st,
132 sc->sc_iwin[0].iwin_base_hi = bus_space_read_4(sc->sc_st,
134 sc->sc_iwin[0].iwin_base_lo =
135 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[0].iwin_base_lo);
139 (0xffffffff - (sc->sc_iwin[1].iwin_size - 1)) & 0xffffffc0);
143 PCI_MAPREG_START + 0x08, sc->sc_iwin[1].iwin_base_lo)
    [all...]
becc.c 120 sc->sc_iwin[0].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT |
123 BECC_CSR_WRITE(BECC_PSTR0, sc->sc_iwin[0].iwin_xlate & PSTRx_ADDRMASK);
126 sc->sc_iwin[1].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT |
129 BECC_CSR_WRITE(BECC_PSTR1, sc->sc_iwin[1].iwin_xlate & PSTRx_ADDRMASK);
136 sc->sc_iwin[2].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT |
140 sc->sc_iwin[2].iwin_xlate & PSTR2_ADDRMASK);
267 dr[i].dr_sysbase = sc->sc_iwin[2].iwin_xlate;
268 dr[i].dr_busbase = sc->sc_iwin[2].iwin_base;
273 dr[i].dr_sysbase = sc->sc_iwin[0].iwin_xlate;
274 dr[i].dr_busbase = sc->sc_iwin[0].iwin_base
    [all...]
beccvar.h 82 } sc_iwin[3]; member in struct:becc_softc
i80321var.h 107 } sc_iwin[4]; member in struct:i80321_softc
i80321_space.c 375 physbase = sc->sc_iwin[1].iwin_xlate;
465 physbase = sc->sc_iwin[1].iwin_xlate;

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