| /src/sys/arch/arm/sunxi/ |
| sunxi_de2_ccu.c | 49 static struct sunxi_ccu_reset sun8i_h3_de2_ccu_resets[] = {
50 SUNXI_CCU_RESET(DE2_RST_MIXER0, 0x08, 0),
51 SUNXI_CCU_RESET(DE2_RST_WB, 0x08, 2),
54 static struct sunxi_ccu_reset sun50i_a64_de2_ccu_resets[] = {
55 SUNXI_CCU_RESET(DE2_RST_MIXER0, 0x08, 0),
56 SUNXI_CCU_RESET(DE2_RST_MIXER1, 0x08, 1),
57 SUNXI_CCU_RESET(DE2_RST_WB, 0x08, 2),
80 struct sunxi_ccu_reset *resets;
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| sun8i_h3_r_ccu.c | 59 static struct sunxi_ccu_reset sun8i_h3_r_ccu_resets[] = {
60 SUNXI_CCU_RESET(H3_R_RST_APB0_IR, APB0_RESET_REG, 1),
61 SUNXI_CCU_RESET(H3_R_RST_APB0_TIMER, APB0_RESET_REG, 2),
62 SUNXI_CCU_RESET(H3_R_RST_APB0_UART, APB0_RESET_REG, 4),
63 SUNXI_CCU_RESET(H3_R_RST_APB0_I2C, APB0_RESET_REG, 6),
|
| sun9i_a80_mmcclk.c | 55 static struct sunxi_ccu_reset sun9i_a80_mmcclk_resets[] = {
56 SUNXI_CCU_RESET(0, SDC_COMM(0), 18),
57 SUNXI_CCU_RESET(1, SDC_COMM(1), 18),
58 SUNXI_CCU_RESET(2, SDC_COMM(2), 18),
59 SUNXI_CCU_RESET(3, SDC_COMM(3), 18),
|
| sunxi_ccu.c | 51 struct sunxi_ccu_reset *reset;
77 struct sunxi_ccu_reset * const reset = priv;
89 struct sunxi_ccu_reset * const reset = priv;
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| sun50i_a64_r_ccu.c | 60 static struct sunxi_ccu_reset sun50i_a64_r_ccu_resets[] = {
61 SUNXI_CCU_RESET(A64_R_RST_APB0_IR, APB0_RESET_REG, 1),
62 SUNXI_CCU_RESET(A64_R_RST_APB0_TIMER, APB0_RESET_REG, 2),
63 SUNXI_CCU_RESET(A64_R_RST_APB0_RSB, APB0_RESET_REG, 3),
64 SUNXI_CCU_RESET(A64_R_RST_APB0_UART, APB0_RESET_REG, 4),
65 SUNXI_CCU_RESET(A64_R_RST_APB0_I2C, APB0_RESET_REG, 6),
|
| sun50i_h6_r_ccu.c | 60 static struct sunxi_ccu_reset sun50i_h6_r_ccu_resets[] = {
61 SUNXI_CCU_RESET(H6_R_RST_APB1_TIMER, 0x11c, 16),
62 SUNXI_CCU_RESET(H6_R_RST_APB1_TWD, 0x12c, 16),
63 SUNXI_CCU_RESET(H6_R_RST_APB1_PWM, 0x13c, 16),
64 SUNXI_CCU_RESET(H6_R_RST_APB2_UART, 0x18c, 16),
65 SUNXI_CCU_RESET(H6_R_RST_APB2_I2C, 0x19c, 16),
66 SUNXI_CCU_RESET(H6_R_RST_APB2_RSB, 0x1bc, 16),
67 SUNXI_CCU_RESET(H6_R_RST_APB1_IR, 0x1cc, 16),
68 SUNXI_CCU_RESET(H6_R_RST_APB1_W1, 0x1ec, 16),
|
| sun9i_a80_usbclk.c | 81 static struct sunxi_ccu_reset sun9i_a80_usbclk_resets[] = {
82 SUNXI_CCU_RESET(RST_USB0_HCI, HCI_SCR, 17),
83 SUNXI_CCU_RESET(RST_USB1_HCI, HCI_SCR, 18),
84 SUNXI_CCU_RESET(RST_USB2_HCI, HCI_SCR, 19),
85 SUNXI_CCU_RESET(RST_USB0_PHY, HCI_PCR, 17),
87 SUNXI_CCU_RESET(RST_USB1_HSIC, HCI_PCR, 18),
88 SUNXI_CCU_RESET(RST_USB1_PHY, HCI_PCR, 19),
89 SUNXI_CCU_RESET(RST_USB2_HSIC, HCI_PCR, 20),
90 SUNXI_CCU_RESET(RST_USB2_PHY, HCI_PCR, 21),
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| sunxi_ccu.h | 36 struct sunxi_ccu_reset;
42 struct sunxi_ccu_reset { struct
47 #define SUNXI_CCU_RESET(_id, _reg, _bit) \
484 struct sunxi_ccu_reset *sc_resets;
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| sun5i_a13_ccu.c | 78 static struct sunxi_ccu_reset sun5i_a13_ccu_resets[] = {
79 SUNXI_CCU_RESET(A13_RST_USB_PHY0, USBPHY_CFG_REG, 0),
80 SUNXI_CCU_RESET(A13_RST_USB_PHY1, USBPHY_CFG_REG, 1),
84 SUNXI_CCU_RESET(A13_RST_DE_BE, BE_CFG_REG, 30),
86 SUNXI_CCU_RESET(A13_RST_DE_FE, FE_CFG_REG, 30),
92 SUNXI_CCU_RESET(A13_RST_CSI, CSI_CFG_REG, 30),
94 SUNXI_CCU_RESET(A13_RST_VE, VE_CFG_REG, 0),
96 SUNXI_CCU_RESET(A13_RST_GPU, MALI_CLOCK_CFG_REG, 30),
98 SUNXI_CCU_RESET(A13_RST_IEP, IEP_SCLK_CFG_REG, 30),
|
| sun6i_a31_ccu.c | 75 static struct sunxi_ccu_reset sun6i_a31_ccu_resets[] = {
76 SUNXI_CCU_RESET(A31_RST_USB_PHY0, USBPHY_CFG_REG, 0),
77 SUNXI_CCU_RESET(A31_RST_USB_PHY1, USBPHY_CFG_REG, 1),
78 SUNXI_CCU_RESET(A31_RST_USB_PHY2, USBPHY_CFG_REG, 2),
80 SUNXI_CCU_RESET(A31_RST_AHB1_MIPI_DSI, BUS_SOFT_RST_REG0, 1),
81 SUNXI_CCU_RESET(A31_RST_AHB1_SS, BUS_SOFT_RST_REG0, 5),
82 SUNXI_CCU_RESET(A31_RST_AHB1_DMA, BUS_SOFT_RST_REG0, 6),
83 SUNXI_CCU_RESET(A31_RST_AHB1_MMC0, BUS_SOFT_RST_REG0, 8),
84 SUNXI_CCU_RESET(A31_RST_AHB1_MMC1, BUS_SOFT_RST_REG0, 9),
85 SUNXI_CCU_RESET(A31_RST_AHB1_MMC2, BUS_SOFT_RST_REG0, 10)
[all...] |
| sun8i_v3s_ccu.c | 85 static struct sunxi_ccu_reset sun8i_v3s_ccu_resets[] = {
86 SUNXI_CCU_RESET(V3S_RST_USBPHY, USBPHY_CFG_REG, 0),
88 SUNXI_CCU_RESET(V3S_RST_MBUS, MBUS_RST_REG, 31),
90 SUNXI_CCU_RESET(V3S_RST_BUS_CE, BUS_SOFT_RST_REG0, 5),
91 SUNXI_CCU_RESET(V3S_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6),
92 SUNXI_CCU_RESET(V3S_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8),
93 SUNXI_CCU_RESET(V3S_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9),
94 SUNXI_CCU_RESET(V3S_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10),
95 SUNXI_CCU_RESET(V3S_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14),
96 SUNXI_CCU_RESET(V3S_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17)
[all...] |
| sun50i_h6_ccu.c | 107 static struct sunxi_ccu_reset sun50i_h6_ccu_resets[] = {
108 SUNXI_CCU_RESET(H6_RST_MBUS, MBUS_CFG_REG, 30),
110 SUNXI_CCU_RESET(H6_RST_BUS_DE, DE_BGR_REG, 16),
112 SUNXI_CCU_RESET(H6_RST_BUS_DEINTERLACE, DI_BGR_REG, 16),
114 SUNXI_CCU_RESET(H6_RST_BUS_GPU, GPU_BGR_REG, 16),
116 SUNXI_CCU_RESET(H6_RST_BUS_CE, CE_BGR_REG, 16),
118 SUNXI_CCU_RESET(H6_RST_BUS_VE, VE_BGR_REG, 16),
120 SUNXI_CCU_RESET(H6_RST_BUS_EMCE, EMCE_BGR_REG, 16),
122 SUNXI_CCU_RESET(H6_RST_BUS_VP9, VP9_BGR_REG, 16),
124 SUNXI_CCU_RESET(H6_RST_BUS_DMA, DMA_BGR_REG, 16)
[all...] |
| sun8i_a83t_ccu.c | 80 static struct sunxi_ccu_reset sun8i_a83t_ccu_resets[] = {
81 SUNXI_CCU_RESET(A83T_RST_USB_PHY0, USBPHY_CFG_REG, 0),
82 SUNXI_CCU_RESET(A83T_RST_USB_PHY1, USBPHY_CFG_REG, 1),
84 SUNXI_CCU_RESET(A83T_RST_MBUS, MBUS_RST_REG, 31),
86 SUNXI_CCU_RESET(A83T_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6),
87 SUNXI_CCU_RESET(A83T_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8),
88 SUNXI_CCU_RESET(A83T_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9),
89 SUNXI_CCU_RESET(A83T_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10),
90 SUNXI_CCU_RESET(A83T_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13),
91 SUNXI_CCU_RESET(A83T_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14)
[all...] |
| sun8i_h3_ccu.c | 91 static struct sunxi_ccu_reset sun8i_h3_ccu_resets[] = {
92 SUNXI_CCU_RESET(H3_RST_USB_PHY0, USBPHY_CFG_REG, 0),
93 SUNXI_CCU_RESET(H3_RST_USB_PHY1, USBPHY_CFG_REG, 1),
94 SUNXI_CCU_RESET(H3_RST_USB_PHY2, USBPHY_CFG_REG, 2),
95 SUNXI_CCU_RESET(H3_RST_USB_PHY3, USBPHY_CFG_REG, 3),
97 SUNXI_CCU_RESET(H3_RST_MBUS, MBUS_RST_REG, 31),
99 SUNXI_CCU_RESET(H3_RST_BUS_CE, BUS_SOFT_RST_REG0, 5),
100 SUNXI_CCU_RESET(H3_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6),
101 SUNXI_CCU_RESET(H3_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8),
102 SUNXI_CCU_RESET(H3_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9)
[all...] |
| sun9i_a80_ccu.c | 84 static struct sunxi_ccu_reset sun9i_a80_ccu_resets[] = {
85 SUNXI_CCU_RESET(A80_RST_BUS_FD, BUS_SOFT_RST_REG0, 0),
86 SUNXI_CCU_RESET(A80_RST_BUS_GPU_CTRL, BUS_SOFT_RST_REG0, 3),
87 SUNXI_CCU_RESET(A80_RST_BUS_SS, BUS_SOFT_RST_REG0, 5),
88 SUNXI_CCU_RESET(A80_RST_BUS_MMC, BUS_SOFT_RST_REG0, 8),
89 SUNXI_CCU_RESET(A80_RST_BUS_NAND1, BUS_SOFT_RST_REG0, 12),
90 SUNXI_CCU_RESET(A80_RST_BUS_NAND0, BUS_SOFT_RST_REG0, 13),
91 SUNXI_CCU_RESET(A80_RST_BUS_TS, BUS_SOFT_RST_REG0, 18),
92 SUNXI_CCU_RESET(A80_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20),
93 SUNXI_CCU_RESET(A80_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21)
[all...] |
| sun50i_a64_ccu.c | 97 static struct sunxi_ccu_reset sun50i_a64_ccu_resets[] = {
98 SUNXI_CCU_RESET(A64_RST_USB_PHY0, USBPHY_CFG_REG, 0),
99 SUNXI_CCU_RESET(A64_RST_USB_PHY1, USBPHY_CFG_REG, 1),
100 SUNXI_CCU_RESET(A64_RST_USB_HSIC, USBPHY_CFG_REG, 2),
102 SUNXI_CCU_RESET(A64_RST_DRAM, DRAM_CFG_REG, 31),
104 SUNXI_CCU_RESET(A64_RST_MBUS, MBUS_RST_REG, 31),
106 SUNXI_CCU_RESET(A64_RST_BUS_MIPI_DSI, BUS_SOFT_RST_REG0, 1),
107 SUNXI_CCU_RESET(A64_RST_BUS_CE, BUS_SOFT_RST_REG0, 5),
108 SUNXI_CCU_RESET(A64_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6),
109 SUNXI_CCU_RESET(A64_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8)
[all...] |
| sun4i_a10_ccu.c | 105 static struct sunxi_ccu_reset sun4i_a10_ccu_resets[] = {
106 SUNXI_CCU_RESET(A10_RST_USB_PHY0, USBPHY_CFG_REG, 0),
107 SUNXI_CCU_RESET(A10_RST_USB_PHY1, USBPHY_CFG_REG, 1),
108 SUNXI_CCU_RESET(A10_RST_USB_PHY2, USBPHY_CFG_REG, 2),
109 SUNXI_CCU_RESET(A10_RST_DE_BE0, BE0_CFG_REG, 30),
110 SUNXI_CCU_RESET(A10_RST_DE_BE1, BE1_CFG_REG, 30),
111 SUNXI_CCU_RESET(A10_RST_DE_FE0, FE0_CFG_REG, 30),
112 SUNXI_CCU_RESET(A10_RST_DE_FE1, FE1_CFG_REG, 30),
113 SUNXI_CCU_RESET(A10_RST_DE_MP, MP_CFG_REG, 30),
114 SUNXI_CCU_RESET(A10_RST_TCON0, LCD0CH0_CFG_REG, 30)
[all...] |
| /src/sys/arch/riscv/sunxi/ |
| sun20i_d1_ccu.c | 111 static struct sunxi_ccu_reset sun20i_d1_ccu_resets[] = {
112 SUNXI_CCU_RESET(D1_RST_MBUS, MBUS_CLK_REG, 30),
114 SUNXI_CCU_RESET(D1_RST_BUS_DE, DE_BGR_REG, 16),
116 SUNXI_CCU_RESET(D1_RST_BUS_DI, DI_BGR_REG, 16),
118 SUNXI_CCU_RESET(D1_RST_BUS_G2D, G2D_BGR_REG, 16),
120 SUNXI_CCU_RESET(D1_RST_BUS_CE, CE_BGR_REG, 16),
122 SUNXI_CCU_RESET(D1_RST_BUS_VE, VE_BGR_REG, 16),
124 SUNXI_CCU_RESET(D1_RST_BUS_DMA, DMA_BGR_REG, 16),
126 SUNXI_CCU_RESET(D1_RST_BUS_MSGBOX0, MSGBOX_BGR_REG, 16),
127 SUNXI_CCU_RESET(D1_RST_BUS_MSGBOX1, MSGBOX_BGR_REG, 17)
[all...] |
