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    Searched refs:vCG_SPLL_FUNC_CNTL (Results 1 - 18 of 18) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
rv770_smc.h 38 uint32_t vCG_SPLL_FUNC_CNTL;
radeon_rv730_dpm.c 114 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
309 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
349 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
radeon_rv740_dpm.c 182 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
387 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
nislands_smc.h 60 uint32_t vCG_SPLL_FUNC_CNTL;
sislands_smc.h 107 uint32_t vCG_SPLL_FUNC_CNTL;
radeon_rv770_dpm.c 561 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
996 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
1056 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
radeon_ni_dpm.c 1715 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1918 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
2063 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
2083 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
2120 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
radeon_cypress_dpm.c 1270 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1453 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
radeon_si_dpm.c 2876 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
4402 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4601 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4845 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4865 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
smu7_hwmgr.h 115 uint32_t vCG_SPLL_FUNC_CNTL;
amdgpu_smu7_hwmgr.c 4287 data->clock_registers.vCG_SPLL_FUNC_CNTL =
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sislands_smc.h 107 uint32_t vCG_SPLL_FUNC_CNTL;
si_dpm.h 369 uint32_t vCG_SPLL_FUNC_CNTL;
711 uint32_t vCG_SPLL_FUNC_CNTL;
amdgpu_si_dpm.c 2975 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
4868 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5066 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5309 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5329 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 867 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1314 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
amdgpu_iceland_smumgr.c 805 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1436 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
amdgpu_ci_smumgr.c 305 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1388 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
amdgpu_tonga_smumgr.c 548 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1188 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;

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