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    Searched refs:vCG_SPLL_FUNC_CNTL_3 (Results 1 - 18 of 18) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
rv770_smc.h 40 uint32_t vCG_SPLL_FUNC_CNTL_3;
radeon_rv730_dpm.c 116 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
311 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
353 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
radeon_rv740_dpm.c 184 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
389 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
nislands_smc.h 62 uint32_t vCG_SPLL_FUNC_CNTL_3;
sislands_smc.h 109 uint32_t vCG_SPLL_FUNC_CNTL_3;
radeon_rv770_dpm.c 563 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
998 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
1060 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
radeon_ni_dpm.c 1719 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1920 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
2065 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
2085 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
2121 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
radeon_cypress_dpm.c 1274 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1457 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
radeon_si_dpm.c 2877 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
4406 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4605 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4847 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4867 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
smu7_hwmgr.h 117 uint32_t vCG_SPLL_FUNC_CNTL_3;
amdgpu_smu7_hwmgr.c 4291 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sislands_smc.h 109 uint32_t vCG_SPLL_FUNC_CNTL_3;
si_dpm.h 371 uint32_t vCG_SPLL_FUNC_CNTL_3;
713 uint32_t vCG_SPLL_FUNC_CNTL_3;
amdgpu_si_dpm.c 2976 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
4872 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5070 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5311 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5331 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 868 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1359 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
amdgpu_iceland_smumgr.c 806 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1475 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
amdgpu_ci_smumgr.c 306 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1427 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
amdgpu_tonga_smumgr.c 549 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1224 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;

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