Searched refs:ver (Results 1 - 25 of 846) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_gfx_ver_enum.h43 #define GFX_LT(ver) ((ver) - 1)
44 #define GFX_GE(ver) (~GFX_LT(ver))
45 #define GFX_LE(ver) (GFX_LT(ver) | (ver))
H A Dbrw_inst.h62 if (devinfo->ver >= 12) \
72 if (devinfo->ver >= 12) \
86 if (devinfo->ver >= 12) { \
88 } else if (devinfo->ver >= 8) { \
90 } else if (devinfo->ver >= 7) { \
92 } else if (devinfo->ver >= 6) { \
94 } else if (devinfo->ver >= 5) { \
147 if (devinfo->ver >= 12) { \
162 if (devinfo->ver >= 12) { \
196 if (devinfo->ver >
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H A Dbrw_compiler.c112 devinfo->ver >= 12 ||
113 (devinfo->ver >= 9 && INTEL_DEBUG(DEBUG_TCS_EIGHT_PATCH));
120 compiler->scalar_stage[i] = devinfo->ver >= 8 ||
154 if (devinfo->ver < 8 || devinfo->ver > 9)
161 devinfo->ver < 6 ? 16 : UINT_MAX;
183 nir_options->lower_ffma16 = devinfo->ver < 6;
184 nir_options->lower_ffma32 = devinfo->ver < 6;
185 nir_options->lower_ffma64 = devinfo->ver < 6;
186 nir_options->lower_flrp32 = devinfo->ver <
[all...]
H A Dbrw_ir_performance.cpp360 if (devinfo->ver >= 11) {
363 } else if (devinfo->ver >= 8) {
385 if (devinfo->ver >= 11) {
388 } else if (devinfo->ver >= 8) {
402 } else if (devinfo->ver >= 7) {
419 if (devinfo->ver >= 11)
422 else if (devinfo->ver >= 8)
428 else if (devinfo->ver >= 7)
435 if (devinfo->ver >= 11) {
438 } else if (devinfo->ver >
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H A Dbrw_eu.h297 if (devinfo->ver >= 5) {
310 if (devinfo->ver >= 5)
319 if (devinfo->ver >= 5)
330 assert(devinfo->ver >= 5);
355 if (devinfo->ver >= 8) {
360 } else if (devinfo->ver >= 7) {
374 assert(devinfo->ver >= 7);
399 if (devinfo->ver >= 7)
402 else if (devinfo->ver >= 5)
430 if (devinfo->ver >
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H A Dbrw_reg_type.c332 } else if (devinfo->ver >= 12) {
335 } else if (devinfo->ver >= 11) {
338 } else if (devinfo->ver >= 8) {
341 } else if (devinfo->ver >= 7) {
344 } else if (devinfo->ver >= 6) {
374 } else if (devinfo->ver >= 12) {
376 } else if (devinfo->ver >= 11) {
378 } else if (devinfo->ver >= 8) {
380 } else if (devinfo->ver >= 7) {
382 } else if (devinfo->ver >
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H A Dbrw_fs_generator.cpp64 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver));
232 if (devinfo->ver >= 6) {
255 if (devinfo->ver >= 6) {
265 if (devinfo->ver < 6) {
282 if (devinfo->ver == 4 && !devinfo->is_g4x) {
346 devinfo->ver >= 12 ? BRW_OPCODE_SENDC : BRW_OPCODE_SENDSC);
363 if (devinfo->ver < 6) {
393 if (devinfo->ver >= 6)
406 devinfo->ver < 6 ? payload : brw_null_reg();
415 assert(devinfo->ver <
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H A Dbrw_eu_emit.c51 if (devinfo->ver < 6)
58 assert(devinfo->ver < 12);
82 if (devinfo->ver >= 7 && reg->file == BRW_MESSAGE_REGISTER_FILE) {
94 assert((dest.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver));
112 if (devinfo->ver >= 12 &&
128 assert(devinfo->ver < 12);
198 if (devinfo->ver >= 6)
214 assert((reg.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver));
220 if (devinfo->ver >= 6 &&
234 if (devinfo->ver >
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/xsrc/external/mit/MesaLib.old/dist/src/broadcom/common/
H A Dv3d_device_info.h34 uint8_t ver; member in struct:v3d_device_info
/xsrc/external/mit/MesaLib/dist/src/broadcom/common/
H A Dv3d_device_info.c57 devinfo->ver = major * 10 + minor;
65 switch (devinfo->ver) {
73 devinfo->ver / 10,
74 devinfo->ver % 10);
H A Dv3d_device_info.h35 uint8_t ver; member in struct:v3d_device_info
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/
H A Dcrocus_screen.c215 return devinfo->ver == 8;
217 return devinfo->ver <= 5;
220 return devinfo->ver >= 5;
238 return devinfo->ver >= 7;
257 return devinfo->ver >= 6;
266 if (devinfo->ver >= 7)
271 if (devinfo->ver >= 7)
278 return (devinfo->ver >= 6) ? 4 : 0;
280 return devinfo->ver >= 7 ? 2048 : 512;
288 else if (devinfo->ver >
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H A Dcrocus_pipe_control.c64 if (devinfo->ver >= 6 &&
120 assert(devinfo->ver >= 6);
127 if (devinfo->ver >= 8)
163 if (devinfo->ver >= 6) {
215 if (devinfo->ver >= 6) {
303 if (devinfo->ver < 6) {
338 assert(devinfo->ver >= 7);
/xsrc/external/mit/MesaLib/dist/src/intel/isl/
H A Disl_storage_image.c110 return (devinfo->ver >= 9 ? format :
127 return (devinfo->ver >= 9 ? format :
134 return (devinfo->ver >= 9 ? format :
140 return (devinfo->ver >= 9 ? format :
147 return (devinfo->ver >= 9 ? format : ISL_FORMAT_R16_UINT);
151 return (devinfo->ver >= 9 ? format : ISL_FORMAT_R8_UINT);
164 return (devinfo->ver >= 11 ? format :
171 return (devinfo->ver >= 11 ? format :
177 return (devinfo->ver >= 11 ? format :
183 return (devinfo->ver >
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/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A Dbrw_pipe_control.c41 if (devinfo->ver >= 6 &&
95 assert(devinfo->ver >= 6);
102 if (devinfo->ver >= 8)
123 assert(devinfo->ver == 7);
277 if (devinfo->ver >= 6) {
362 if (devinfo->ver >= 6) {
399 switch (devinfo->ver) {
429 if (devinfo->ver < 6)
H A Dbrw_misc_state.c59 if (devinfo->ver == 5) {
222 if (devinfo->ver >= 6)
290 const unsigned len = (devinfo->is_g4x || devinfo->ver == 5) ? 6 : 5;
310 if (devinfo->is_g4x || devinfo->ver >= 5)
315 if (devinfo->ver >= 6)
338 if (devinfo->ver < 6) {
398 if (devinfo->ver == 6) {
432 if (devinfo->ver == 6) {
472 const bool is_965 = devinfo->ver == 4 && !devinfo->is_g4x;
476 if (devinfo->ver >
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H A Dbrw_extensions.c42 assert(devinfo->ver >= 4);
145 if (devinfo->ver >= 8)
149 else if (devinfo->ver >= 7 && can_do_pipelined_register_writes(brw->screen))
151 else if (devinfo->ver >= 6)
156 if (devinfo->ver >= 6)
166 if (devinfo->is_g4x || devinfo->ver >= 5) {
171 if (devinfo->ver >= 5) {
177 if (devinfo->ver == 6)
180 if (devinfo->ver >= 6) {
237 if (devinfo->ver >
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H A Dgfx7_sol_state.c46 assert(brw->screen->devinfo.ver == 7);
109 assert(brw->screen->devinfo.ver == 7);
136 assert(brw->screen->devinfo.ver == 7);
H A Dbrw_formatquery.c40 switch (devinfo->ver) {
81 assert(devinfo->ver < 6);
/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/ddc/
H A DddcProperty.c63 } else if (DDC->ver.version == 1) {
65 } else if (DDC->ver.version == 2) {
96 DDC->ver.version, DDC->ver.revision);
/xsrc/external/mit/MesaLib/dist/src/broadcom/drm-shim/
H A Dv3d.c93 v3d.devinfo->ver = v3d_hw_get_version(v3d.hw);
95 if (v3d.devinfo->ver >= 42)
97 else if (v3d.devinfo->ver >= 41)
/xsrc/external/mit/MesaLib/dist/src/broadcom/qpu/tests/
H A Dqpu_disasm.c33 int ver; member in struct:__anon6fccbb800108
126 devinfo.ver = tests[i].ver;
129 devinfo.ver / 10, devinfo.ver % 10,
/xsrc/external/mit/MesaLib.old/dist/src/broadcom/qpu/tests/
H A Dqpu_disasm.c32 int ver; member in struct:__anon40aebb8d0108
125 devinfo.ver = tests[i].ver;
128 devinfo.ver / 10, devinfo.ver % 10,
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/v3d/
H A Dv3d_formats.c43 if (devinfo->ver >= 41)
137 if (devinfo->ver >= 41) {
150 if (devinfo->ver >= 41) {
/xsrc/external/mit/MesaLib/dist/src/intel/common/
H A Dintel_l3_config.c166 switch (devinfo->ver) {
265 w.w[INTEL_L3P_SLM] = devinfo->ver < 11 && needs_slm;
268 if (devinfo->ver >= 8) {
288 assert(list->length > 0 || devinfo->ver >= 12);
322 assert(cfg_best || devinfo->ver >= 12);
333 (devinfo->ver >= 9 && devinfo->l3_banks == 1) || devinfo->ver >= 11 ?
347 return (devinfo->ver >= 8 ? devinfo->num_slices : 1);
366 const unsigned max = (devinfo->ver == 9 ? 1008 : ~0);

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