Searched refs:BLENDFACTOR_INV_SRC_ALPHA (Results 1 - 25 of 51) sorted by relevance

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/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di830_render.c110 {0, 1, BLENDFACTOR_ONE, BLENDFACTOR_INV_SRC_ALPHA},
120 {0, 1, BLENDFACTOR_ZERO, BLENDFACTOR_INV_SRC_ALPHA},
122 {1, 1, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
126 {1, 1, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
214 } else if (dblend == BLENDFACTOR_INV_SRC_ALPHA) {
H A Di830_reg.h299 #define BLENDFACTOR_INV_SRC_ALPHA 0x06 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di830_render.c110 {0, 1, BLENDFACTOR_ONE, BLENDFACTOR_INV_SRC_ALPHA},
120 {0, 1, BLENDFACTOR_ZERO, BLENDFACTOR_INV_SRC_ALPHA},
122 {1, 1, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
126 {1, 1, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
214 } else if (dblend == BLENDFACTOR_INV_SRC_ALPHA) {
H A Di830_reg.h293 #define BLENDFACTOR_INV_SRC_ALPHA 0x06 macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di830_render.c108 {0, 1, BLENDFACTOR_ONE, BLENDFACTOR_INV_SRC_ALPHA},
118 {0, 1, BLENDFACTOR_ZERO, BLENDFACTOR_INV_SRC_ALPHA},
120 {1, 1, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
124 {1, 1, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
213 } else if (dblend == BLENDFACTOR_INV_SRC_ALPHA) {
H A Di830_reg.h229 #define BLENDFACTOR_INV_SRC_ALPHA 0x06 macro
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/
H A Dswr_state.h296 return BLENDFACTOR_INV_SRC_ALPHA;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/
H A Dswr_state.h319 return BLENDFACTOR_INV_SRC_ALPHA;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/core/core/
H A Dblend.h85 case BLENDFACTOR_INV_SRC_ALPHA:
H A Dstate.h491 BLENDFACTOR_INV_SRC_ALPHA, enumerator in enum:SWR_BLEND_FACTOR
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen2_render.h222 #define BLENDFACTOR_INV_SRC_ALPHA 0x06 macro
H A Dgen8_render.c192 /* Over */ {1, BLENDFACTOR_ONE, BLENDFACTOR_INV_SRC_ALPHA},
197 /* OutReverse */ {1, BLENDFACTOR_ZERO, BLENDFACTOR_INV_SRC_ALPHA},
198 /* Atop */ {1, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
200 /* Xor */ {1, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
341 else if (dst == BLENDFACTOR_INV_SRC_ALPHA)
H A Dgen9_render.c209 /* Over */ {1, BLENDFACTOR_ONE, BLENDFACTOR_INV_SRC_ALPHA},
214 /* OutReverse */ {1, BLENDFACTOR_ZERO, BLENDFACTOR_INV_SRC_ALPHA},
215 /* Atop */ {1, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
217 /* Xor */ {1, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
392 else if (dst == BLENDFACTOR_INV_SRC_ALPHA)
H A Dgen8_render.h372 #define BLENDFACTOR_INV_SRC_ALPHA 0x13 macro
H A Dgen9_render.h381 #define BLENDFACTOR_INV_SRC_ALPHA 0x13 macro
H A Dgen2_render.c72 {0, 1, BLENDFACTOR_ONE, BLENDFACTOR_INV_SRC_ALPHA},
82 {0, 1, BLENDFACTOR_ZERO, BLENDFACTOR_INV_SRC_ALPHA},
84 {1, 1, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
88 {1, 1, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
465 else if (dblend == BLENDFACTOR_INV_SRC_ALPHA)
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di830_reg.h293 #define BLENDFACTOR_INV_SRC_ALPHA 0x06 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen2_render.h222 #define BLENDFACTOR_INV_SRC_ALPHA 0x06 macro
H A Dgen2_render.c69 {0, 1, BLENDFACTOR_ONE, BLENDFACTOR_INV_SRC_ALPHA},
79 {0, 1, BLENDFACTOR_ZERO, BLENDFACTOR_INV_SRC_ALPHA},
81 {1, 1, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
85 {1, 1, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
462 else if (dblend == BLENDFACTOR_INV_SRC_ALPHA)
H A Dgen8_render.c153 /* Over */ {1, BLENDFACTOR_ONE, BLENDFACTOR_INV_SRC_ALPHA},
158 /* OutReverse */ {1, BLENDFACTOR_ZERO, BLENDFACTOR_INV_SRC_ALPHA},
159 /* Atop */ {1, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
161 /* Xor */ {1, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_INV_SRC_ALPHA},
275 else if (dst == BLENDFACTOR_INV_SRC_ALPHA)
H A Dgen8_render.h371 #define BLENDFACTOR_INV_SRC_ALPHA 0x13 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di830_reg.h293 #define BLENDFACTOR_INV_SRC_ALPHA 0x06 macro
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/jitter/
H A Dblend_jit.cpp114 case BLENDFACTOR_INV_SRC_ALPHA:
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/rasterizer/jitter/
H A Dblend_jit.cpp116 case BLENDFACTOR_INV_SRC_ALPHA:
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A DgenX_pipeline.c641 [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA] = BLENDFACTOR_INV_SRC_ALPHA,

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