Searched refs:BRW_VERTICAL_STRIDE_0 (Results 1 - 25 of 29) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_reg.h520 BRW_VERTICAL_STRIDE_0,
627 BRW_VERTICAL_STRIDE_0,
748 imm.vstride = BRW_VERTICAL_STRIDE_0;
871 BRW_VERTICAL_STRIDE_0,
1238 region_matches(reg, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_1, \
1253 assert(reg.vstride != BRW_VERTICAL_STRIDE_0);
H A Dbrw_disasm.c1162 case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0;
1192 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0;
1209 if (_vert_stride == BRW_VERTICAL_STRIDE_0 &&
1219 case BRW_VERTICAL_STRIDE_0:
1298 _vert_stride = BRW_VERTICAL_STRIDE_0;
1307 is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 &&
1372 _vert_stride = BRW_VERTICAL_STRIDE_0;
1381 is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 &&
1460 _vert_stride = BRW_VERTICAL_STRIDE_0;
1469 is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0
[all...]
H A Dbrw_eu_emit.c303 brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0);
410 brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0);
768 case BRW_VERTICAL_STRIDE_0:
965 src0.vstride == BRW_VERTICAL_STRIDE_0);
974 src1.vstride == BRW_VERTICAL_STRIDE_0);
983 src2.vstride == BRW_VERTICAL_STRIDE_0);
1045 if (src0.vstride == BRW_VERTICAL_STRIDE_0) \
1047 if (src1.vstride == BRW_VERTICAL_STRIDE_0) \
1049 if (src2.vstride == BRW_VERTICAL_STRIDE_0) \
1075 if (src0.vstride == BRW_VERTICAL_STRIDE_0) \
[all...]
H A Dbrw_eu_validate.c205 return brw_inst_src0_vstride(devinfo, inst) == BRW_VERTICAL_STRIDE_0 &&
214 return brw_inst_src1_vstride(devinfo, inst) == BRW_VERTICAL_STRIDE_0 &&
951 brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 &&
957 brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 &&
966 brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 &&
972 brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 &&
H A Dtest_eu_validate.cpp217 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
681 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
690 brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
727 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
736 brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
834 { BRW_VERTICAL_STRIDE_0, true },
1127 brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
1144 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
H A Dbrw_vec4.cpp1940 BRW_VERTICAL_STRIDE_0,
2149 if (inst->src[i].vstride == BRW_VERTICAL_STRIDE_0 &&
2675 hw_reg->vstride = BRW_VERTICAL_STRIDE_0;
2686 hw_reg->vstride = BRW_VERTICAL_STRIDE_0;
H A Dbrw_eu_defines.h1040 BRW_VERTICAL_STRIDE_0 = 0, enumerator in enum:brw_vertical_stride
/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_disasm.c993 case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0;
1019 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0;
1036 if (_vert_stride == BRW_VERTICAL_STRIDE_0 &&
1046 case BRW_VERTICAL_STRIDE_0:
1122 _vert_stride = BRW_VERTICAL_STRIDE_0;
1131 is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 &&
1190 _vert_stride = BRW_VERTICAL_STRIDE_0;
1199 is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 &&
1272 _vert_stride = BRW_VERTICAL_STRIDE_0;
1281 is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0
[all...]
H A Dbrw_reg.h527 BRW_VERTICAL_STRIDE_0,
634 BRW_VERTICAL_STRIDE_0,
755 imm.vstride = BRW_VERTICAL_STRIDE_0;
878 BRW_VERTICAL_STRIDE_0,
1224 region_matches(reg, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_1, \
H A Dbrw_eu_validate.c196 return brw_inst_src0_vstride(devinfo, inst) == BRW_VERTICAL_STRIDE_0 &&
204 return brw_inst_src1_vstride(devinfo, inst) == BRW_VERTICAL_STRIDE_0 &&
864 brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 &&
870 brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 &&
879 brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 &&
885 brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 &&
H A Dbrw_eu_emit.c272 brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0);
375 brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0);
668 case BRW_VERTICAL_STRIDE_0:
828 src0.vstride == BRW_VERTICAL_STRIDE_0);
837 src1.vstride == BRW_VERTICAL_STRIDE_0);
846 src2.vstride == BRW_VERTICAL_STRIDE_0);
908 if (src0.vstride == BRW_VERTICAL_STRIDE_0) \
910 if (src1.vstride == BRW_VERTICAL_STRIDE_0) \
912 if (src2.vstride == BRW_VERTICAL_STRIDE_0) \
938 if (src0.vstride == BRW_VERTICAL_STRIDE_0) \
[all...]
H A Dbrw_eu_defines.h966 BRW_VERTICAL_STRIDE_0 = 0, enumerator in enum:brw_vertical_stride
H A Dtest_eu_validate.cpp288 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
297 brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
334 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
343 brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
441 { BRW_VERTICAL_STRIDE_0, true },
734 brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
751 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
H A Dbrw_vec4.cpp1918 BRW_VERTICAL_STRIDE_0,
2118 if (inst->src[i].vstride == BRW_VERTICAL_STRIDE_0 &&
2644 hw_reg->vstride = BRW_VERTICAL_STRIDE_0;
2655 hw_reg->vstride = BRW_VERTICAL_STRIDE_0;
/xsrc/external/mit/xf86-video-intel/dist/src/sna/brw/
H A Dbrw_eu.h300 #define BRW_VERTICAL_STRIDE_0 0 macro
1336 BRW_VERTICAL_STRIDE_0,
1427 BRW_VERTICAL_STRIDE_0,
1482 imm.vstride = BRW_VERTICAL_STRIDE_0;
1493 imm.vstride = BRW_VERTICAL_STRIDE_0;
1510 imm.vstride = BRW_VERTICAL_STRIDE_0;
1604 BRW_VERTICAL_STRIDE_0,
H A Dbrw_eu_emit.c282 insn->bits2.da1.src0_vert_stride = BRW_VERTICAL_STRIDE_0;
346 insn->bits3.da1.src1_vert_stride = BRW_VERTICAL_STRIDE_0;
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/brw/
H A Dbrw_eu.h300 #define BRW_VERTICAL_STRIDE_0 0 macro
1336 BRW_VERTICAL_STRIDE_0,
1427 BRW_VERTICAL_STRIDE_0,
1482 imm.vstride = BRW_VERTICAL_STRIDE_0;
1493 imm.vstride = BRW_VERTICAL_STRIDE_0;
1510 imm.vstride = BRW_VERTICAL_STRIDE_0;
1604 BRW_VERTICAL_STRIDE_0,
H A Dbrw_eu_emit.c282 insn->bits2.da1.src0_vert_stride = BRW_VERTICAL_STRIDE_0;
346 insn->bits3.da1.src1_vert_stride = BRW_VERTICAL_STRIDE_0;
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Dbrw_defines.h672 #define BRW_VERTICAL_STRIDE_0 0 macro
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Dbrw_defines.h672 #define BRW_VERTICAL_STRIDE_0 0 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Dbrw_defines.h672 #define BRW_VERTICAL_STRIDE_0 0 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Dbrw_defines.h672 #define BRW_VERTICAL_STRIDE_0 0 macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Dbrw_defines.h665 #define BRW_VERTICAL_STRIDE_0 0 macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen8_eu.c474 __gen8_set_src0_vert_stride(inst, BRW_VERTICAL_STRIDE_0);
545 __gen8_set_src1_vert_stride(inst, BRW_VERTICAL_STRIDE_0);
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen8_eu.c474 __gen8_set_src0_vert_stride(inst, BRW_VERTICAL_STRIDE_0);
545 __gen8_set_src1_vert_stride(inst, BRW_VERTICAL_STRIDE_0);

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