Searched refs:CP_PACKET0 (Results 1 - 25 of 30) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r300/
H A Dr300_cb.h132 OUT_CB(CP_PACKET0(register, 0)); \
140 OUT_CB(CP_PACKET0(register, (count) - 1)); \
145 OUT_CB(CP_PACKET0(register, (count) - 1) | RADEON_ONE_REG_WR); \
H A Dr300_cs.h83 OUT_CS(CP_PACKET0(register, 0)); \
90 OUT_CS(CP_PACKET0((register), ((count) - 1)))
93 OUT_CS(CP_PACKET0((register), ((count) - 1)) | RADEON_ONE_REG_WR)
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r300/
H A Dr300_cb.h132 OUT_CB(CP_PACKET0(register, 0)); \
140 OUT_CB(CP_PACKET0(register, (count) - 1)); \
145 OUT_CB(CP_PACKET0(register, (count) - 1) | RADEON_ONE_REG_WR); \
H A Dr300_cs.h83 OUT_CS(CP_PACKET0(register, 0)); \
90 OUT_CS(CP_PACKET0((register), ((count) - 1)))
93 OUT_CS(CP_PACKET0((register), ((count) - 1)) | RADEON_ONE_REG_WR)
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/
H A Dradeon_state_init.c164 return CP_PACKET0(packet[id].start, packet[id].len - 1);
244 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
246 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
255 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
376 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
380 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
383 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
387 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
389 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
394 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSE
[all...]
H A Dradeon_cmdbuf.h19 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) macro
H A Dradeon_ioctl.c102 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0));
104 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
107 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
113 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0));
H A Dradeon_blit.c37 return CP_PACKET0(reg, count - 1);
H A Dradeon_context.c116 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/
H A Dradeon_state_init.c163 return CP_PACKET0(packet[id].start, packet[id].len - 1);
243 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
245 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
254 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
375 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
379 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
382 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
386 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
388 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
393 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSE
[all...]
H A Dradeon_cmdbuf.h19 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) macro
H A Dradeon_ioctl.c101 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0));
103 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
106 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
112 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0));
H A Dradeon_blit.c37 return CP_PACKET0(reg, count - 1);
H A Dradeon_context.c116 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/r200/
H A Dr200_state_init.c169 return CP_PACKET0(packet[id].start, packet[id].len - 1);
282 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
284 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
298 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
300 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
311 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
320 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
494 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
498 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
501 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITC
[all...]
H A Dr200_context.c151 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
H A Dr200_blit.c37 return CP_PACKET0(reg, count - 1);
H A Dr200_cmdbuf.c215 OUT_BATCH(CP_PACKET0(R200_SE_VF_MAX_VTX_INDX, 0));
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/r200/
H A Dr200_state_init.c169 return CP_PACKET0(packet[id].start, packet[id].len - 1);
282 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
284 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
298 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
300 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
311 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
320 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
494 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
498 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
501 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITC
[all...]
H A Dr200_context.c152 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
/xsrc/external/mit/xf86-video-ati/dist/src/
H A Dradeon.h1414 #define CP_PACKET0(reg, n) \ macro
1491 OUT_RING(CP_PACKET0(reg, 0)); \
1519 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
1530 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
1545 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
1558 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1561 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1573 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1576 OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); \
H A Devergreen_state.h288 E32(CP_PACKET0 ((reg), (num) - 1)); \
H A Dr600_state.h274 E32((ib), CP_PACKET0 ((reg), (num) - 1)); \
/xsrc/external/mit/xf86-video-ati-kms/dist/src/
H A Devergreen_state.h284 E32(CP_PACKET0 ((reg), (num) - 1)); \
H A Dr600_state.h248 E32(CP_PACKET0 ((reg), (num) - 1)); \

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