Searched refs:DCFlushEnable (Results 1 - 22 of 22) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A DgenX_pipe_control.c468 pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH;
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A DgenX_pipe_control.c472 pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH;
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A DgenX_state.c71 pc.DCFlushEnable = true;
H A DgenX_cmd_buffer.c69 pc.DCFlushEnable = true;
1591 pc.DCFlushEnable = true;
1622 pc.DCFlushEnable = true;
1754 pipe.DCFlushEnable = bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT;
3790 pc.DCFlushEnable = true;
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A DgenX_cmd_buffer.c58 bits |= (pc->DCFlushEnable) ? ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0;
111 pc.DCFlushEnable = true;
2071 pc.DCFlushEnable = true;
2104 pc.DCFlushEnable = true;
2219 pipe.DCFlushEnable |= bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
2222 pipe.DCFlushEnable |= bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT;
2291 !pipe.DCFlushEnable)
5447 pc.DCFlushEnable = true;
/xsrc/external/mit/MesaLib.old/src/intel/genxml/
H A Dgen7_pack.h6185 bool DCFlushEnable; member in struct:GEN7_PIPE_CONTROL
6233 __gen_uint(values->DCFlushEnable, 5, 5) |
H A Dgen10_pack.h9860 bool DCFlushEnable; member in struct:GEN10_PIPE_CONTROL
9910 __gen_uint(values->DCFlushEnable, 5, 5) |
H A Dgen11_pack.h9945 bool DCFlushEnable; member in struct:GEN11_PIPE_CONTROL
9995 __gen_uint(values->DCFlushEnable, 5, 5) |
H A Dgen75_pack.h7483 bool DCFlushEnable; member in struct:GEN75_PIPE_CONTROL
7531 __gen_uint(values->DCFlushEnable, 5, 5) |
H A Dgen8_pack.h8286 bool DCFlushEnable; member in struct:GEN8_PIPE_CONTROL
8334 __gen_uint(values->DCFlushEnable, 5, 5) |
H A Dgen9_pack.h9832 bool DCFlushEnable; member in struct:GEN9_PIPE_CONTROL
9881 __gen_uint(values->DCFlushEnable, 5, 5) |
/xsrc/external/mit/MesaLib/src/intel/genxml/
H A Dgen7_pack.h6201 bool DCFlushEnable; member in struct:GFX7_PIPE_CONTROL
6249 __gen_uint(values->DCFlushEnable, 5, 5) |
H A Dgen10_pack.h9860 bool DCFlushEnable; member in struct:GEN10_PIPE_CONTROL
9910 __gen_uint(values->DCFlushEnable, 5, 5) |
H A Dgen11_pack.h10430 bool DCFlushEnable; member in struct:GFX11_PIPE_CONTROL
10482 __gen_uint(values->DCFlushEnable, 5, 5) |
H A Dgen75_pack.h7499 bool DCFlushEnable; member in struct:GFX75_PIPE_CONTROL
7547 __gen_uint(values->DCFlushEnable, 5, 5) |
H A Dgen8_pack.h8302 bool DCFlushEnable; member in struct:GFX8_PIPE_CONTROL
8350 __gen_uint(values->DCFlushEnable, 5, 5) |
H A Dgen9_pack.h9848 bool DCFlushEnable; member in struct:GFX9_PIPE_CONTROL
9897 __gen_uint(values->DCFlushEnable, 5, 5) |
H A Dgen125_pack.h10927 bool DCFlushEnable; member in struct:GFX125_PIPE_CONTROL
10983 __gen_uint(values->DCFlushEnable, 5, 5) |
H A Dgen12_pack.h11272 bool DCFlushEnable; member in struct:GFX12_PIPE_CONTROL
11328 __gen_uint(values->DCFlushEnable, 5, 5) |
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/iris/
H A Diris_state.c6280 pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/
H A Diris_state.c7852 pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/
H A Dcrocus_state.c8860 pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH;

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