| /xsrc/external/mit/xorg-server/dist/hw/xfree86/x86emu/x86emu/ |
| x86emui.h | 79 # undef DS
|
| regs.h | 114 * CS, DS, ES, SS.
119 # undef DS
127 u16 CS, DS, SS, ES, FS, GS;
170 #define R_DS seg.DS
270 * SEGMENT overrides 5 bits normal,DS,SS,CS,ES
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a4xx/ |
| fd4_program.c | 133 DS = 3,
146 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
193 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
194 s[HS].constoff = s[DS].constoff = s[GS].constoff = s[FS].constoff;
291 OUT_RING(ring, A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(s[DS].constlen) |
292 A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
293 A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(s[DS].instrlen) |
294 A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s[DS].instroff));
414 OUT_RING(ring, A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
415 A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[DS].instroff))
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a5xx/ |
| fd5_program.c | 164 enum { VS = 0, FS = 1, HS = 2, DS = 3, GS = 4, MAX_STAGES };
174 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
225 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
308 OUT_RING(ring, A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) |
309 A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) |
310 COND(s[DS].v, A5XX_HLSQ_DS_CONFIG_ENABLED));
328 OUT_RING(ring, A5XX_HLSQ_DS_CNTL_INSTRLEN(s[DS].instrlen) |
329 COND(s[DS].v && s[DS].v->has_ssbo,
345 OUT_RING(ring, A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff)
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a5xx/ |
| fd5_program.c | 253 DS = 3,
266 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
316 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
376 OUT_RING(ring, A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) |
377 A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) |
378 COND(s[DS].v, A5XX_HLSQ_DS_CONFIG_ENABLED));
393 OUT_RING(ring, A5XX_HLSQ_DS_CNTL_INSTRLEN(s[DS].instrlen) |
394 COND(s[DS].v && s[DS].v->has_ssbo, A5XX_HLSQ_DS_CNTL_SSBO_ENABLE));
408 OUT_RING(ring, A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff)
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a4xx/ |
| fd4_program.c | 91 enum { VS = 0, FS = 1, HS = 2, DS = 3, GS = 4, MAX_STAGES };
101 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
149 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
150 s[HS].constoff = s[DS].constoff = s[GS].constoff = s[FS].constoff;
261 A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(s[DS].constlen) |
262 A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
263 A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(s[DS].instrlen) |
264 A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s[DS].instroff));
396 OUT_RING(ring, A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
397 A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[DS].instroff))
[all...] |
| /xsrc/external/mit/xorg-server.old/dist/hw/xfree86/x86emu/x86emu/ |
| regs.h | 112 * CS, DS, ES, SS.
116 u16 CS, DS, SS, ES, FS, GS;
167 #define R_DS seg.DS
267 * SEGMENT overrides 5 bits normal,DS,SS,CS,ES
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a6xx/ |
| fd6_program.c | 251 DS = 3,
271 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
379 OUT_RING(ring, COND(s[DS].v, A6XX_SP_DS_CONFIG_ENABLED)); /* SP_DS_CONFIG */
380 OUT_RING(ring, s[DS].instrlen); /* SP_DS_INSTRLEN */
414 OUT_RING(ring, A6XX_HLSQ_DS_CNTL_CONSTLEN(s[DS].constlen)); /* HLSQ_DS_CONSTLEN */
|
| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| aco_opt_value_numbering.cpp | 99 case Format::DS: return hash_murmur_32<DS_instruction>(instr);
235 case Format::DS: {
238 DS_instruction& aD = a->ds();
239 DS_instruction& bD = b->ds();
334 case Format::DS:
|
| aco_opcodes.py | 46 DS = 15
60 DS = 8
91 elif self == Format.DS:
1122 # DS instructions: 3 inputs (1 addr, 2 data), 1 output
1123 DS = {
1280 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in DS:
1281 opcode(name, gfx7, gfx9, gfx10, Format.DS, InstrClass.DS)
|
| aco_statistics.cpp | 137 case instr_class::ds:
138 return instr->ds().gds ? perf_info{0, WAIT_USE(export_gds, 1)}
166 case instr_class::ds:
167 return instr->ds().gds ? perf_info{4, WAIT_USE(export_gds, 4)}
246 if (instr->format == Format::DS)
343 case instr_class::ds:
|
| aco_insert_waitcnt.cpp | 282 (it->second.events & lgkm_events) == (instr->ds().gds ? event_gds : event_lds))
657 case Format::DS: {
658 DS_instruction& ds = instr->ds(); local
659 update_counters(ctx, ds.gds ? event_gds : event_lds, ds.sync);
660 if (ds.gds)
664 insert_wait_entry(ctx, instr->definitions[0], ds.gds ? event_gds : event_lds);
666 if (ds.gds) {
|
| aco_ir.cpp | 179 case Format::DS: return instr->ds().sync;
|
| aco_print_ir.cpp | 353 case Format::DS: {
354 const DS_instruction& ds = instr->ds(); local
355 if (ds.offset0)
356 fprintf(output, " offset0:%u", ds.offset0);
357 if (ds.offset1)
358 fprintf(output, " offset1:%u", ds.offset1);
359 if (ds.gds)
361 print_sync(ds.sync, output);
|
| aco_ir.h | 80 DS = 8,
125 ds = 15, member in class:aco::instr_class
1098 DS_instruction& ds() noexcept
1103 const DS_instruction& ds() const noexcept
1108 constexpr bool isDS() const noexcept { return format == Format::DS; }
|
| aco_assembler.cpp | 352 case Format::DS: {
353 DS_instruction& ds = instr->ds(); local
357 encoding |= (ds.gds ? 1 : 0) << 16;
360 encoding |= (ds.gds ? 1 : 0) << 17;
362 encoding |= ((0xFF & ds.offset1) << 8);
363 encoding |= (0xFFFF & ds.offset0);
|
| /xsrc/external/mit/MesaLib/dist/src/intel/vulkan/ |
| genX_gpu_memcpy.c | 133 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DS), DS);
|
| /xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/ |
| genX_gpu_memcpy.c | 122 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DS), DS);
|
| /xsrc/external/mit/xorg-server/dist/hw/xfree86/x86emu/ |
| decode.c | 44 # undef DS
255 On the x86 processor, the default segment is not always DS if there is
259 whether the access is relative to DS or SS. That is the function of the
266 ds segment override
272 ds/ss select (in absence of override)
281 case 0: /* default case: use ds register */
712 DECODE_PRINTF("DS");
836 NOTE: The code which specifies the corresponding segment (ds vs ss)
842 if a SS access is needed, set this bit. Otherwise, DS access
|
| /xsrc/external/mit/MesaLib/dist/src/util/ |
| 00-mesa-defaults.conf | 474 <application name="Citra - Nintendo 3DS Emulator" executable="citra-qt">
|
| /xsrc/external/mit/MesaLib.old/dist/src/intel/blorp/ |
| blorp_genX_exec.h | 1093 struct GENX(3DSTATE_WM_DEPTH_STENCIL) ds = {
1097 struct GENX(DEPTH_STENCIL_STATE) ds = { 0 };
1101 ds.DepthBufferWriteEnable = true;
1105 ds.DepthTestEnable = true;
1106 ds.DepthTestFunction = COMPAREFUNCTION_ALWAYS;
1115 ds.DepthTestEnable = true;
1116 ds.DepthTestFunction = COMPAREFUNCTION_NEVER;
1121 ds.DepthTestEnable = false;
1129 ds.StencilBufferWriteEnable = true;
1130 ds.StencilTestEnable = true
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/intel/blorp/ |
| blorp_genX_exec.h | 1171 struct GENX(3DSTATE_WM_DEPTH_STENCIL) ds = {
1175 struct GENX(DEPTH_STENCIL_STATE) ds = { 0 };
1179 ds.DepthBufferWriteEnable = true;
1188 ds.DepthTestEnable = true;
1189 ds.DepthTestFunction = COMPAREFUNCTION_NEVER;
1195 ds.DepthTestEnable = false;
1203 ds.StencilBufferWriteEnable = true;
1204 ds.StencilTestEnable = true;
1205 ds.DoubleSidedStencilEnable = false;
1207 ds.StencilTestFunction = COMPAREFUNCTION_ALWAYS
[all...] |
| /xsrc/external/mit/evieext/dist/ |
| config.guess | 1249 DS/*:UNIX_System_V:*:*)
|
| /xsrc/external/mit/xf86-input-ws/dist/ |
| config.guess | 1213 DS/*:UNIX_System_V:*:*)
|
| /xsrc/external/mit/font-adobe-utopia-75dpi/dist/ |
| config.guess | 1267 DS/*:UNIX_System_V:*:*)
|
