Searched refs:DacRegs (Results 1 - 17 of 17) sorted by relevance

/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/ramdac/
H A DTI.c160 if (ramdacReg->DacRegs[TIDAC_PIXEL_VALID]) {
168 ramdacReg->DacRegs[TIDAC_PIXEL_N]);
170 ramdacReg->DacRegs[TIDAC_PIXEL_M]);
172 ramdacReg->DacRegs[TIDAC_PIXEL_P]);
186 if (ramdacReg->DacRegs[TIDAC_LOOP_VALID]) {
194 ramdacReg->DacRegs[TIDAC_LOOP_N]);
196 ramdacReg->DacRegs[TIDAC_LOOP_M]);
198 ramdacReg->DacRegs[TIDAC_LOOP_P]);
238 ramdacReg->DacRegs[TIDAC_PIXEL_N] =
241 ramdacReg->DacRegs[TIDAC_PIXEL_
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H A DTIPriv.h22 ramdacReg->DacRegs[_reg] = (*ramdacPtr->ReadDAC)(pScrn, _reg); \
27 (ramdacReg->DacRegs[_reg] & 0xFF00) >> 8, \
28 ramdacReg->DacRegs[_reg]); \
H A DIBM.c195 (pScrn, i, (ramdacReg->DacRegs[i] & 0xFF00) >> 8,
196 ramdacReg->DacRegs[i]);
225 ramdacReg->DacRegs[i] = (*ramdacPtr->ReadDAC)(pScrn, i);
324 ramdacReg->DacRegs[IBMRGB_key_control] = 0x00; /* Disable Chroma Key */
328 ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_32BPP;
329 ramdacReg->DacRegs[IBMRGB_32bpp] = B32_DCOL_DIRECT;
330 ramdacReg->DacRegs[IBMRGB_24bpp] = 0;
331 ramdacReg->DacRegs[IBMRGB_16bpp] = 0;
332 ramdacReg->DacRegs[IBMRGB_8bpp] = 0;
334 ramdacReg->DacRegs[IBMRGB_key_contro
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H A DBT.c49 (pScrn, i, (ramdacReg->DacRegs[i] & 0xFF00) >> 8,
50 ramdacReg->DacRegs[i]);
65 ramdacReg->DacRegs[i] = (*ramdacPtr->ReadDAC)(pScrn, i);
147 ramdacReg->DacRegs[BT_COMMAND_REG_1] = 0x10;
150 ramdacReg->DacRegs[BT_COMMAND_REG_1] = 0x10;
153 ramdacReg->DacRegs[BT_COMMAND_REG_1] = 0x38;
156 ramdacReg->DacRegs[BT_COMMAND_REG_1] = 0x30;
159 ramdacReg->DacRegs[BT_COMMAND_REG_1] = 0x40;
162 ramdacReg->DacRegs[BT_COMMAND_REG_1] = 0x60;
H A Dxf86RamDac.h19 unsigned short DacRegs[0x400]; /* register set */ member in struct:_RamDacRegRec
/xsrc/external/mit/xf86-video-glint/dist/src/
H A Dpm_dac.c104 ramdacReg->DacRegs[IBMRGB_m0] = m;
105 ramdacReg->DacRegs[IBMRGB_n0] = n;
106 ramdacReg->DacRegs[IBMRGB_p0] = p;
107 ramdacReg->DacRegs[IBMRGB_c0] = c;
109 ramdacReg->DacRegs[IBMRGB_pll_ctrl1] = 0x05;
110 ramdacReg->DacRegs[IBMRGB_pll_ctrl2] = 0x00;
116 ramdacReg->DacRegs[IBMRGB_sysclk] = 0x05;
117 ramdacReg->DacRegs[IBMRGB_sysclk_m] = m;
118 ramdacReg->DacRegs[IBMRGB_sysclk_n] = n;
119 ramdacReg->DacRegs[IBMRGB_sysclk_
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H A Dpm2v_dac.c217 pReg->DacRegs[PM2VDACRDDACControl] = 0x00;
225 pReg->DacRegs[PM2VDACRDDClk0PreScale] = m;
226 pReg->DacRegs[PM2VDACRDDClk0FeedbackScale] = n;
227 pReg->DacRegs[PM2VDACRDDClk0PostScale] = p;
233 pReg->DacRegs[PM2VDACRDMiscControl] = 0x01; /* 8bit DAC */
235 pReg->DacRegs[PM2VDACRDMiscControl] = 0x00; /* 6bit DAC */
237 pReg->DacRegs[PM2VDACRDSyncControl] = 0x00;
239 pReg->DacRegs[PM2VDACRDSyncControl] |= 0x01; /* invert hsync */
241 pReg->DacRegs[PM2VDACRDSyncControl] |= 0x08; /* invert vsync */
246 pReg->DacRegs[PM2VDACRDPixelSiz
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H A Dpm2_dac.c169 pReg->DacRegs[PM2DACIndexMDCR] = 0x00; /* Disable Overlay */
177 pReg->DacRegs[PM2DACIndexClockAM] = m;
178 pReg->DacRegs[PM2DACIndexClockAN] = n;
179 pReg->DacRegs[PM2DACIndexClockAP] = p|0x08;
183 pReg->DacRegs[PM2DACIndexMCR] = 0x02; /* 8bit DAC */
185 pReg->DacRegs[PM2DACIndexMCR] = 0x00; /* 6bit DAC */
188 pReg->DacRegs[PM2DACIndexMCR] |= 0x04; /* invert hsync */
190 pReg->DacRegs[PM2DACIndexMCR] |= 0x08; /* invert vsync */
195 pReg->DacRegs[PM2DACIndexCMR] = PM2DAC_RGB | PM2DAC_GRAPHICS |
200 pReg->DacRegs[PM2DACIndexCM
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H A Dglint_regs.h1332 pReg->DacRegs[address] = value;
1335 Permedia2vOutIndReg(pScrn, address, 0x00, pReg->DacRegs[address]);
1338 pReg->DacRegs[address] = Permedia2vInIndReg(pScrn, address);
1343 ramdacReg->DacRegs[address] = value;
H A Dglint.h66 CARD32 DacRegs[0x1000]; member in struct:__anon125efece0108
/xsrc/external/mit/xf86-video-mga/dist/src/
H A Dmga_dacG.c1058 pReg->DacRegs[ MGA1064_PIX_PLLC_M ] = m;
1059 pReg->DacRegs[ MGA1064_PIX_PLLC_N ] = n;
1060 pReg->DacRegs[ MGA1064_PIX_PLLC_P ] = p;
1103 pReg->DacRegs[ MGA1064_PIX_PLLC_M ] = m & 0x1F;
1104 pReg->DacRegs[ MGA1064_PIX_PLLC_N ] = n & 0x7F;
1105 pReg->DacRegs[ MGA1064_PIX_PLLC_P ] = (p & 0x07) |
1162 /* Allocate the DacRegs space if not done already */
1163 if (pReg->DacRegs == NULL) {
1164 pReg->DacRegs = xnfcalloc(DACREGSIZE, 1);
1167 pReg->DacRegs[
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H A Dmga_dac3026.c466 pReg->DacRegs[ 18 ] = lq | 0x38;
514 /* Allocate the DacRegs space if not done already */
515 if (pReg->DacRegs == NULL) {
516 pReg->DacRegs = xnfcalloc(DACREGSIZE, 1);
519 pReg->DacRegs[i] = initDAC[i];
526 pReg->DacRegs[1] &= ~0x01;
528 if (pMga->Interleave ) pReg->DacRegs[2] += 1;
533 /* we need to set DacRegs[0] differently based on the silicon
547 pReg->DacRegs[0] = 0x07;
550 pReg->DacRegs[
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H A Dmga_dh.c261 pReg->DacRegs[MGA1064_GEN_IO_CTL] = ucByte;
266 pReg->DacRegs[MGA1064_GEN_IO_DATA]= ucByte;
H A Dmga.h218 unsigned char * DacRegs; member in struct:__anon971c52dc0208
/xsrc/external/mit/xf86-video-tga/dist/src/
H A Dtga_dac.c744 ramdacReg->DacRegs[BT_COMMAND_REG_0] = 0xA0 |
747 ramdacReg->DacRegs[BT_COMMAND_REG_2] = 0x20;
749 ramdacReg->DacRegs[BT_COMMAND_REG_2] = 0x27; /* ?? was 0x20 */
751 ramdacReg->DacRegs[BT_STATUS_REG] = 0x14;
/xsrc/external/mit/xf86-video-trident/dist/src/
H A Dtrident.h90 unsigned char DacRegs[0x300]; member in struct:__anon52c1ffc60108
/xsrc/external/mit/xf86-video-ag10e/dist/src/
H A Dglint_regs.h1339 pReg->DacRegs[address] = value;
1342 Permedia2vOutIndReg(pScrn, address, 0x00, pReg->DacRegs[address]);
1345 pReg->DacRegs[address] = Permedia2vInIndReg(pScrn, address);
1350 ramdacReg->DacRegs[address] = value;

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