Searched refs:L1 (Results 1 - 14 of 14) sorted by relevance
| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| H A D | README-ISA.md | 126 ## RDNA L0, L1 cache and DLC, GLC bits
128 The old L1 cache was renamed to L0, and a new L1 cache was added to RDNA. The
129 L1 cache is 1 cache per shader array. Some instruction encodings have DLC and
132 * DLC ("device level coherent") bit: controls the L1 cache
139 Stores and atomics always bypass the L1 cache, so they don't support the DLC bit,
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| /xsrc/external/mit/MesaLib.old/dist/src/mesa/main/ |
| H A D | texcompress_astc.cpp | 1008 int s0, s1, L0, L1; local in function:Block::decode_colour_endpoints
1018 L1 = L0 + (v1 & 0x3f);
1019 if (L1 > 0xff)
1020 L1 = 0xff;
1022 e1 = uint8x4_t(L1, L1, L1, 0xff);
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| /xsrc/external/mit/MesaLib/dist/src/mesa/main/ |
| H A D | texcompress_astc.cpp | 1009 int s0, s1, L0, L1; local in function:Block::decode_colour_endpoints
1019 L1 = L0 + (v1 & 0x3f);
1020 if (L1 > 0xff)
1021 L1 = 0xff;
1023 e1 = uint8x4_t(L1, L1, L1, 0xff);
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| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 13.0.3.rst | 108 - radeonsi: apply a TC L1 write corruption workaround for SI
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| H A D | 17.3.3.rst | 62 - radv: Invalidate L1 for VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT.
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| H A D | 17.1.6.rst | 75 - radv/ac: port SI TC L1 write corruption fix.
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| H A D | 19.0.0.rst | 2296 - ac/nir: don't trash L1 caches for store operations with writeonly
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| H A D | 20.2.0.rst | 3229 - ac/nir: honor ACCESS_STREAM_CACHE_POLICY for L1 and L0 caches too
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| H A D | 20.3.0.rst | 3135 - isl: Enable Tigerlake HDC:L1 caches via MOCS in various cases.
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| /xsrc/external/mit/xorg-server.old/dist/hw/xfree86/ddc/ |
| H A D | edid.h | 115 #define L1 _L1(GET_ARRAY(V_MANUFACTURER)) macro
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| H A D | interpret_edid.c | 345 r->name[0] = L1;
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| /xsrc/external/mit/xorg-server/dist/hw/xfree86/ddc/ |
| H A D | edid.h | 114 #define L1 _L1(GET_ARRAY(V_MANUFACTURER)) macro
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| H A D | interpret_edid.c | 443 r->name[0] = L1;
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| /xsrc/external/mit/MesaLib/dist/ |
| H A D | .pick_status.json | 11056 "description": "intel/genxml: Add L1 Cache Control bit field",
16222 "description": "isl: Don't enable HDC:L1 caches on DG2",
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