Searched refs:MI_BATCH_BUFFER_END (Results 1 - 25 of 46) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/intel/tools/
H A Dgen10_context.h75 *data++ = MI_BATCH_BUFFER_END | 1 /* End Context */;
125 *data++ = MI_BATCH_BUFFER_END | 1 /* End Context */;
165 *data++ = MI_BATCH_BUFFER_END | 1 /* End Context */;
H A Dgen8_context.h73 *data++ = MI_BATCH_BUFFER_END;
115 *data++ = MI_BATCH_BUFFER_END;
155 *data++ = MI_BATCH_BUFFER_END;
H A Dgen_context.h44 #define MI_BATCH_BUFFER_END (0xA << 23) macro
/xsrc/external/mit/MesaLib/dist/src/intel/tools/
H A Dgfx10_context.h75 *data++ = MI_BATCH_BUFFER_END | 1 /* End Context */;
125 *data++ = MI_BATCH_BUFFER_END | 1 /* End Context */;
165 *data++ = MI_BATCH_BUFFER_END | 1 /* End Context */;
H A Dgfx8_context.h73 *data++ = MI_BATCH_BUFFER_END;
115 *data++ = MI_BATCH_BUFFER_END;
155 *data++ = MI_BATCH_BUFFER_END;
H A Dintel_context.h44 #define MI_BATCH_BUFFER_END (0xA << 23) macro
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Dintel_batchbuffer.c50 #define MI_BATCH_BUFFER_END (0xA << 23) macro
61 *(unsigned int *)xvmc_driver->batch.ptr = MI_BATCH_BUFFER_END;
H A Dbrw_defines.h40 #define MI_BATCH_BUFFER_END 0x0A
H A Di830_reg.h46 #define MI_BATCH_BUFFER_END (0xA << 23) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Dintel_batchbuffer.c50 #define MI_BATCH_BUFFER_END (0xA << 23) macro
61 *(unsigned int *)xvmc_driver->batch.ptr = MI_BATCH_BUFFER_END;
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dsna_reg.h17 #define MI_BATCH_BUFFER_END (0xA << 23) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dsna_reg.h17 #define MI_BATCH_BUFFER_END (0xA << 23) macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/xvmc/
H A Dintel_batchbuffer.c50 #define MI_BATCH_BUFFER_END (0xA << 23) macro
94 *(unsigned int*)xvmc_driver->batch.ptr = MI_BATCH_BUFFER_END;
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di830_batchbuffer.c199 *(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = MI_BATCH_BUFFER_END;
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Dintel_reg.h34 #define MI_BATCH_BUFFER_END (CMD_MI | 0xA << 23) macro
H A Dintel_batchbuffer.c166 intel_batchbuffer_emit_dword(intel, MI_BATCH_BUFFER_END);
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Dintel_reg.h34 #define MI_BATCH_BUFFER_END (CMD_MI | 0xA << 23) macro
H A Dintel_batchbuffer.c166 intel_batchbuffer_emit_dword(intel, MI_BATCH_BUFFER_END);
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Dintel_batchbuffer.c260 OUT_BATCH(MI_BATCH_BUFFER_END);
H A Dbrw_defines.h40 #define MI_BATCH_BUFFER_END 0x0A
H A Di830_reg.h46 #define MI_BATCH_BUFFER_END (0xA << 23) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Dintel_batchbuffer.c249 OUT_BATCH(MI_BATCH_BUFFER_END);
H A Dbrw_defines.h40 #define MI_BATCH_BUFFER_END 0x0A
H A Di830_reg.h46 #define MI_BATCH_BUFFER_END (0xA << 23) macro
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A DgenX_state.c243 anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);

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