Searched refs:MI_FLUSH (Results 1 - 25 of 51) sorted by relevance

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/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dsna_reg.h5 #define MI_FLUSH (0x04<<23) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dsna_reg.h5 #define MI_FLUSH (0x04<<23) macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di830_accel.c160 OUT_BATCH(MI_FLUSH | flags);
H A Di830_batchbuffer.c188 *(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = MI_FLUSH | flags;
H A Di915_video.c95 OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
376 OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
H A Dbrw_defines.h37 #define MI_FLUSH 0x04
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Dintel_reg.h36 #define MI_FLUSH (CMD_MI | (4 << 23)) macro
H A Dintel_batchbuffer.c263 OUT_BATCH(MI_FLUSH);
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Dintel_reg.h36 #define MI_FLUSH (CMD_MI | (4 << 23)) macro
H A Dintel_batchbuffer.c263 OUT_BATCH(MI_FLUSH);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/
H A Di915_state_emit.c66 OUT_BATCH(MI_FLUSH | FLUSH_MAP_CACHE);
68 OUT_BATCH(MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE);
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Dintel_batchbuffer.c225 OUT_BATCH(MI_FLUSH | flags);
H A Dbrw_defines.h37 #define MI_FLUSH 0x04
H A Di830_reg.h34 #define MI_FLUSH (0x04<<23) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Dintel_batchbuffer.c225 OUT_BATCH(MI_FLUSH | flags);
H A Dbrw_defines.h37 #define MI_FLUSH 0x04
H A Di830_reg.h34 #define MI_FLUSH (0x04<<23) macro
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/
H A Di915_state_emit.c68 OUT_BATCH(MI_FLUSH | FLUSH_MAP_CACHE);
70 OUT_BATCH(MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE);
H A Di915_reg.h861 #define MI_FLUSH ((0<<29)|(4<<23)) macro
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A Dbrw_misc_state.c62 OUT_BATCH(MI_FLUSH);
550 * MI_FLUSH or PIPE_CONTROL prior to the execution of PIPELINE_SELECT.
553 OUT_BATCH(MI_FLUSH);
659 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A Dbrw_misc_state.c62 OUT_BATCH(MI_FLUSH);
549 * MI_FLUSH or PIPE_CONTROL prior to the execution of PIPELINE_SELECT.
552 OUT_BATCH(MI_FLUSH);
748 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Dbrw_defines.h37 #define MI_FLUSH 0x04
H A Di830_reg.h34 #define MI_FLUSH (0x04<<23) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Dbrw_defines.h37 #define MI_FLUSH 0x04
H A Di830_reg.h34 #define MI_FLUSH (0x04<<23) macro

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