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    Searched refs:MMIOBase (Results 1 - 25 of 46) sorted by relevancy

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  /xsrc/external/mit/xf86-video-chips/dist/src/
ct_BlitMM.h 34 while(MMIO_IN32(cPtr->MMIOBase, MR(0x4)) & 0x00100000){};}
37 {HW_DEBUG(0x4); MMIO_OUT32(cPtr->MMIOBase, MR(0x4), op);}
41 MMIO_OUT32(cPtr->MMIOBase, MR(0x5),(srcAddr)&0x7FFFFFL);}
45 MMIO_OUT32(cPtr->MMIOBase, MR(0x6), (dstAddr)&0x7FFFFFL);}
49 MMIO_OUT32(cPtr->MMIOBase, MR(0x0),(((dstPitch)&0xFFFF)<<16)| \
54 MMIO_OUT32(cPtr->MMIOBase, MR(0x7), (((Height)&0xFFFF)<<16)| \
59 MMIO_OUT32(cPtr->MMIOBase, MR(0x1),(srcAddr)&0x1FFFFFL);}
65 MMIO_OUT32(cPtr->MMIOBase, MR(0x2),\
75 MMIO_OUT32(cPtr->MMIOBase, MR(0x2), \
86 MMIO_OUT32(cPtr->MMIOBase, MR(0x2),((c)&0xFFFFFF));
    [all...]
ct_BltHiQV.h 75 if (!(MMIO_IN32(cPtr->MMIOBase,BR(0x4))&(1<<31)))\
106 if (!(MMIO_IN32(cPtr->MMIOBase,BR(0x4))&(1<<31)))\
127 if (!(MMIO_IN32(cPtr->MMIOBase,BR(0x4))&(1<<31)))\
152 MMIO_OUT32(cPtr->MMIOBase, BR(0x4), op)
155 MMIO_OUT32(cPtr->MMIOBase, BR(0x3), op)
158 MMIO_OUT32(cPtr->MMIOBase, BR(0x6), (srcAddr)&0x7FFFFFL)
161 MMIO_OUT32(cPtr->MMIOBase, BR(0x7), (dstAddr)&0x7FFFFFL)
164 MMIO_OUT32(cPtr->MMIOBase, BR(0x0), (((dstPitch)&0xFFFF)<<16)| \
168 MMIO_OUT32(cPtr->MMIOBase, BR(0x8), (((Height)&0xFFFF)<<16)| \
172 MMIO_OUT32(cPtr->MMIOBase, BR(0x5), (srcAddr)&0x7FFFFFL
    [all...]
ct_regs.c 247 * <value> determines which MMIOBase to use; either
255 hwp->MMIOBase = cPtr->MMIOBaseVGA;
302 #define minb(p) MMIO_IN8(hwp->MMIOBase, (p))
303 #define moutb(p,v) MMIO_OUT8(hwp->MMIOBase, (p),(v))
517 hwp->MMIOBase = base;
ct_driver.h 150 #define MMIOmeml(x) *(CARD32 *)(cPtr->MMIOBase + (x))
152 #define MMIOmemw(x) *(CARD16 *)(cPtr->MMIOBase + (x))
290 unsigned char * MMIOBase;
  /xsrc/external/mit/xf86-video-i740/dist/src/
i740.h 53 #define INREG8(addr) *(volatile CARD8 *)(pI740->MMIOBase + (addr))
54 #define INREG16(addr) *(volatile CARD16 *)(pI740->MMIOBase + (addr))
55 #define INREG(addr) *(volatile CARD32 *)(pI740->MMIOBase + (addr))
56 #define OUTREG8(addr, val) *(volatile CARD8 *)(pI740->MMIOBase + (addr)) = (val)
57 #define OUTREG16(addr, val) *(volatile CARD16 *)(pI740->MMIOBase + (addr)) = (val)
58 #define OUTREG(addr, val) *(volatile CARD32 *)(pI740->MMIOBase + (addr)) = (val)
99 unsigned char *MMIOBase;
168 #define minb(p) MMIO_IN8(pI740->MMIOBase, (p))
169 #define moutb(p,v) MMIO_OUT8(pI740->MMIOBase, (p),(v))
  /xsrc/external/mit/xf86-video-tdfx/dist/src/
tdfx_io.c 87 moutb(pTDFX->MMIOBase[0], addr, index);
88 moutb(pTDFX->MMIOBase[0], addr+1, val);
92 moutb(pTDFX->MMIOBase[0], addr, index);
93 return minb(pTDFX->MMIOBase[0], addr+1);
97 moutl(pTDFX->MMIOBase[chip], addr, val);
101 return minl(pTDFX->MMIOBase[chip], addr);
113 if (!pTDFX->MMIOBase[0])
114 ErrorF("Can not set MMIO access before MMIOBase[0]\n");
tdfx.h 206 void *MMIOBase[MAXCHIPS];
209 unsigned char *MMIOBase[MAXCHIPS];
  /xsrc/external/mit/xf86-video-nv/dist/src/
riva_setup.c 37 RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
43 RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
49 RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
55 RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
61 RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
67 RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
73 RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
86 RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
99 RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
104 RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
    [all...]
nv_setup.c 43 NVPtr pNv = (NVPtr)pVga->MMIOBase;
49 NVPtr pNv = (NVPtr)pVga->MMIOBase;
55 NVPtr pNv = (NVPtr)pVga->MMIOBase;
61 NVPtr pNv = (NVPtr)pVga->MMIOBase;
67 NVPtr pNv = (NVPtr)pVga->MMIOBase;
73 NVPtr pNv = (NVPtr)pVga->MMIOBase;
79 NVPtr pNv = (NVPtr)pVga->MMIOBase;
92 NVPtr pNv = (NVPtr)pVga->MMIOBase;
105 NVPtr pNv = (NVPtr)pVga->MMIOBase;
110 NVPtr pNv = (NVPtr)pVga->MMIOBase;
    [all...]
  /xsrc/external/mit/xf86-video-mach64/dist/src/
atividmem.c 347 unsigned long MMIOBase = pATI->Block0Base & ~(PageSize - 1);
352 Tag, MMIOBase, PageSize);
365 err = pci_device_map_range(pVideo, MMIOBase,
401 (pATI->Block0Base - MMIOBase);
413 if ((pATI->CursorBase >= MMIOBase) &&
414 ((pATI->CursorBase + 0x00000400UL) <= (MMIOBase + PageSize)))
416 (pATI->CursorBase - MMIOBase);
  /xsrc/external/mit/xf86-video-openchrome/dist/src/
via_vgahw.c 46 if (hwp->MMIOBase)
47 return MMIO_IN8(hwp->MMIOBase, hwp->MMIOOffset + address);
55 if (hwp->MMIOBase)
56 MMIO_OUT8(hwp->MMIOBase, hwp->MMIOOffset + address, value);
  /xsrc/external/mit/xf86-video-ark/dist/src/
ark_reg.h 82 *(volatile unsigned short *)(pARK->MMIOBase + offset) = value
84 *(volatile unsigned int *)(pARK->MMIOBase + offset) = value
ark.h 46 pointer MMIOBase;
  /xsrc/external/mit/xf86-video-intel/dist/src/legacy/i810/
i810_common.h 84 #define INREG8(addr) *(volatile uint8_t *)(RecPtr->MMIOBase + (addr))
85 #define INREG16(addr) *(volatile uint16_t *)(RecPtr->MMIOBase + (addr))
86 #define INREG(addr) *(volatile uint32_t *)(RecPtr->MMIOBase + (addr))
91 *(volatile uint8_t *)(RecPtr->MMIOBase + (addr)) = (val); \
99 *(volatile uint16_t *)(RecPtr->MMIOBase + (addr)) = (val); \
107 *(volatile uint32_t *)(RecPtr->MMIOBase + (addr)) = (val); \
i810.h 131 unsigned char *MMIOBase;
  /xsrc/external/mit/xf86-video-intel-2014/dist/src/legacy/i810/
i810_common.h 84 #define INREG8(addr) *(volatile uint8_t *)(RecPtr->MMIOBase + (addr))
85 #define INREG16(addr) *(volatile uint16_t *)(RecPtr->MMIOBase + (addr))
86 #define INREG(addr) *(volatile uint32_t *)(RecPtr->MMIOBase + (addr))
91 *(volatile uint8_t *)(RecPtr->MMIOBase + (addr)) = (val); \
99 *(volatile uint16_t *)(RecPtr->MMIOBase + (addr)) = (val); \
107 *(volatile uint32_t *)(RecPtr->MMIOBase + (addr)) = (val); \
i810.h 131 unsigned char *MMIOBase;
  /xsrc/external/mit/xf86-video-imstt/dist/src/
imstt_reg.h 31 #define INREG(addr) regr(((unsigned long)(iptr->MMIOBase)), (addr))
32 #define OUTREG(addr, val) regw(((unsigned long)(iptr->MMIOBase)), (addr), (val))
36 #define INREG(addr) MMIO_IN32(iptr->MMIOBase, addr)
37 #define OUTREG(addr, val) MMIO_OUT32(iptr->MMIOBase, addr, val)
47 unsigned long *IMSTTMMIO = IMSTTPTR(pScrn)->MMIOBase
imstt.h 19 unsigned long * MMIOBase;
  /xsrc/external/mit/xf86-video-intel-old/dist/src/
i810_io.c 60 #define minb(p) *(volatile uint8_t *)(pI810->MMIOBase + (p))
61 #define moutb(p,v) *(volatile uint8_t *)(pI810->MMIOBase + (p)) = (v)
common.h 117 #define INREG8(addr) *(volatile uint8_t *)(RecPtr->MMIOBase + (addr))
118 #define INREG16(addr) *(volatile uint16_t *)(RecPtr->MMIOBase + (addr))
119 #define INREG(addr) *(volatile uint32_t *)(RecPtr->MMIOBase + (addr))
124 *(volatile uint8_t *)(RecPtr->MMIOBase + (addr)) = (val); \
132 *(volatile uint16_t *)(RecPtr->MMIOBase + (addr)) = (val); \
140 *(volatile uint32_t *)(RecPtr->MMIOBase + (addr)) = (val); \
i810.h 144 unsigned char *MMIOBase;
  /xsrc/external/mit/xf86-video-cirrus/dist/src/
alp_xaam.c 30 MMIO_IN8(hwp->MMIOBase, (hwp->MMIOOffset + (p))))
33 MMIO_OUT8(hwp->MMIOBase, (hwp->MMIOOffset + (p)),(v));}
44 #define vga_moutb(p,v) MMIO_OUT8(hwp->MMIOBase, (hwp->MMIOOffset + (p)),(v))
  /xsrc/external/mit/xf86-video-tseng/dist/src/
tseng_mode.c 41 if (hwp->MMIOBase)
42 MMIO_OUT8(hwp->MMIOBase, hwp->MMIOOffset + VGA_BANK, value);
54 if (hwp->MMIOBase)
55 return MMIO_IN8(hwp->MMIOBase, hwp->MMIOOffset + VGA_BANK);
69 if (hwp->MMIOBase)
70 MMIO_OUT8(hwp->MMIOBase, hwp->MMIOOffset + VGA_SEGMENT, value);
82 if (hwp->MMIOBase)
83 return MMIO_IN8(hwp->MMIOBase, hwp->MMIOOffset + VGA_SEGMENT);
100 if (hwp->MMIOBase)
101 MMIO_OUT8(hwp->MMIOBase,
    [all...]
  /xsrc/external/mit/xf86-video-s3/dist/src/
s3.h 121 unsigned char * MMIOBase;

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