Searched refs:PUSH_DATA (Results 1 - 25 of 184) sorted by relevance

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/xsrc/external/mit/xf86-video-nouveau/dist/src/
H A Dnv50_accel.c54 PUSH_DATA (push, pNv->vblank_sem->handle);
55 PUSH_DATA (push, 0);
57 PUSH_DATA (push, 0x22222222);
59 PUSH_DATA (push, 0x11111111);
60 PUSH_DATA (push, head);
62 PUSH_DATA (push, 0x11111111);
80 PUSH_DATA (push, pNv->NvMemFormat->handle);
82 PUSH_DATA (push, pNv->notify0->handle);
84 PUSH_DATA (push, fifo->vram);
85 PUSH_DATA (pus
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H A Dnouveau_copy85b5.c59 PUSH_DATA (push, src->config.nv50.tile_mode);
60 PUSH_DATA (push, src_pitch);
61 PUSH_DATA (push, src_h);
62 PUSH_DATA (push, 1);
63 PUSH_DATA (push, 0);
64 PUSH_DATA (push, src_x * cpp);
65 PUSH_DATA (push, src_y);
67 PUSH_DATA (push, dst->config.nv50.tile_mode);
68 PUSH_DATA (push, dst_pitch);
69 PUSH_DATA (pus
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H A Dnouveau_copy90b5.c59 PUSH_DATA (push, src->config.nvc0.tile_mode);
60 PUSH_DATA (push, src_pitch);
61 PUSH_DATA (push, src_h);
62 PUSH_DATA (push, 1);
63 PUSH_DATA (push, 0);
64 PUSH_DATA (push, src_x * cpp);
65 PUSH_DATA (push, src_y);
67 PUSH_DATA (push, dst->config.nvc0.tile_mode);
68 PUSH_DATA (push, dst_pitch);
69 PUSH_DATA (pus
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H A Dnouveau_copya0b5.c59 PUSH_DATA (push, 0x00001000 | src->config.nvc0.tile_mode);
60 PUSH_DATA (push, src_pitch);
61 PUSH_DATA (push, src_h);
62 PUSH_DATA (push, 1);
63 PUSH_DATA (push, 0);
64 PUSH_DATA (push, (src_y << 16) | src_x * cpp);
66 PUSH_DATA (push, 0x000001000 | dst->config.nvc0.tile_mode);
67 PUSH_DATA (push, dst_pitch);
68 PUSH_DATA (push, dst_h);
69 PUSH_DATA (pus
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H A Dnvc0_accel.h60 PUSH_DATA (push, VTX_ATTR(1, 2, FLOAT, 4));
64 PUSH_DATA (push, VTX_ATTR(0, 2, SSCALED, 4));
65 PUSH_DATA (push, dx);
66 PUSH_DATA (push, dy);
74 PUSH_DATA (push, VTX_ATTR(1, 2, SSCALED, 4));
75 PUSH_DATA (push, x0);
76 PUSH_DATA (push, y0);
78 PUSH_DATA (push, VTX_ATTR(2, 2, SSCALED, 4));
79 PUSH_DATA (push, x1);
80 PUSH_DATA (pus
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H A Dnv50_exa.c86 PUSH_DATA (push, x);
87 PUSH_DATA (push, y);
88 PUSH_DATA (push, w);
89 PUSH_DATA (push, h);
106 PUSH_DATA (push, fmt);
107 PUSH_DATA (push, 1);
109 PUSH_DATA (push, (uint32_t)exaGetPixmapPitch(ppix));
112 PUSH_DATA (push, fmt);
113 PUSH_DATA (push, 0);
114 PUSH_DATA (pus
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H A Dnvc0_accel.c96 PUSH_DATA (push, pNv->NvSW->handle);
98 PUSH_DATA (push, (pNv->scratch->offset + SEMA_OFFSET) >> 32);
99 PUSH_DATA (push, (pNv->scratch->offset + SEMA_OFFSET));
100 PUSH_DATA (push, 0x22222222);
101 PUSH_DATA (push, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
103 PUSH_DATA (push, (pNv->scratch->offset + SEMA_OFFSET) >> 32);
104 PUSH_DATA (push, (pNv->scratch->offset + SEMA_OFFSET));
105 PUSH_DATA (push, 0x11111111);
106 PUSH_DATA (push, head);
108 PUSH_DATA (pus
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H A Dnv10_exa.c408 PUSH_DATA (push, NV10_3D_TEX_ENABLE_ENABLE);
410 PUSH_DATA (push, exaGetPixmapPitch(pixmap) << 16);
412 PUSH_DATA (push, (w << 16) | h);
415 PUSH_DATA(push, NV10_3D_TEX_FILTER_MAGNIFY_NEAREST |
418 PUSH_DATA(push, NV10_3D_TEX_FILTER_MAGNIFY_LINEAR |
422 PUSH_DATA (push, 1);
442 PUSH_DATA (push, 0);
455 PUSH_DATA (push, get_rt_format(pict));
456 PUSH_DATA (push, (exaGetPixmapPitch(pixmap) << 16 |
487 PUSH_DATA (pus
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H A Dnv50_xv.c93 PUSH_DATA (push, dst->offset >> 32);
94 PUSH_DATA (push, dst->offset);
96 case 32: PUSH_DATA (push, NV50_SURFACE_FORMAT_BGRA8_UNORM); break;
97 case 30: PUSH_DATA (push, NV50_SURFACE_FORMAT_RGB10_A2_UNORM); break;
98 case 24: PUSH_DATA (push, NV50_SURFACE_FORMAT_BGRX8_UNORM); break;
99 case 16: PUSH_DATA (push, NV50_SURFACE_FORMAT_B5G6R5_UNORM); break;
100 case 15: PUSH_DATA (push, NV50_SURFACE_FORMAT_BGR5_X1_UNORM); break;
102 PUSH_DATA (push, dst->config.nv50.tile_mode);
103 PUSH_DATA (push, 0);
105 PUSH_DATA (pus
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H A Dnvc0_exa.c88 PUSH_DATA (push, x);
89 PUSH_DATA (push, y);
90 PUSH_DATA (push, w);
91 PUSH_DATA (push, h);
108 PUSH_DATA (push, fmt);
109 PUSH_DATA (push, 1);
111 PUSH_DATA (push, (uint32_t)exaGetPixmapPitch(ppix));
114 PUSH_DATA (push, fmt);
115 PUSH_DATA (push, 0);
116 PUSH_DATA (pus
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H A Dnvc0_xv.c89 PUSH_DATA (push, dst->offset >> 32);
90 PUSH_DATA (push, dst->offset);
91 PUSH_DATA (push, ppix->drawable.width);
92 PUSH_DATA (push, ppix->drawable.height);
94 case 32: PUSH_DATA (push, NV50_SURFACE_FORMAT_BGRA8_UNORM); break;
95 case 30: PUSH_DATA (push, NV50_SURFACE_FORMAT_RGB10_A2_UNORM); break;
96 case 24: PUSH_DATA (push, NV50_SURFACE_FORMAT_BGRX8_UNORM); break;
97 case 16: PUSH_DATA (push, NV50_SURFACE_FORMAT_B5G6R5_UNORM); break;
98 case 15: PUSH_DATA (push, NV50_SURFACE_FORMAT_BGR5_X1_UNORM); break;
100 PUSH_DATA (pus
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H A Dnv40_exa.c171 PUSH_DATA (push, 0);
174 PUSH_DATA (push, 1);
175 PUSH_DATA (push, sblend);
176 PUSH_DATA (push, dblend);
177 PUSH_DATA (push, 0x00000000);
178 PUSH_DATA (push, NV40_3D_BLEND_EQUATION_ALPHA_FUNC_ADD |
189 PUSH_DATA (push, pPict->pSourcePict->solidFill.color);
190 PUSH_DATA (push, 0);
194 PUSH_DATA (push, NV40_3D_TEX_FORMAT_FORMAT_A8R8G8B8 | 0x8000 |
200 PUSH_DATA (pus
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/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/nouveau/
H A Dnv20_context.c68 PUSH_DATA (push, pack_rgba_clamp_f(s->format, ctx->Color.ClearColor.f));
83 PUSH_DATA (push, pack_zs_f(s->format, ctx->Depth.Clear,
90 PUSH_DATA (push, clear);
105 PUSH_DATA (push, hw->eng3d->handle);
107 PUSH_DATA (push, hw->ntfy->handle);
109 PUSH_DATA (push, fifo->vram);
110 PUSH_DATA (push, fifo->gart);
112 PUSH_DATA (push, fifo->vram);
113 PUSH_DATA (push, fifo->vram);
115 PUSH_DATA (pus
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H A Dnv10_context.c155 PUSH_DATA (push, pack_zs_f(s->format, ctx->Depth.Clear, 0));
157 PUSH_DATA (push, 1);
209 PUSH_DATA (push, hw->eng3d->handle);
211 PUSH_DATA (push, hw->ntfy->handle);
214 PUSH_DATA (push, fifo->vram);
215 PUSH_DATA (push, fifo->gart);
216 PUSH_DATA (push, fifo->gart);
218 PUSH_DATA (push, fifo->vram);
219 PUSH_DATA (push, fifo->vram);
222 PUSH_DATA (pus
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H A Dnv20_state_frag.c43 PUSH_DATA (push, a_in);
45 PUSH_DATA (push, a_out);
47 PUSH_DATA (push, c_in);
49 PUSH_DATA (push, c_out);
51 PUSH_DATA (push, k);
66 PUSH_DATA (push, in);
67 PUSH_DATA (push, in >> 32);
70 PUSH_DATA (push, MAX2(1, n));
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/nouveau/
H A Dnv20_context.c69 PUSH_DATA (push, pack_rgba_clamp_f(s->format, ctx->Color.ClearColor.f));
84 PUSH_DATA (push, pack_zs_f(s->format, ctx->Depth.Clear,
91 PUSH_DATA (push, clear);
106 PUSH_DATA (push, hw->eng3d->handle);
108 PUSH_DATA (push, hw->ntfy->handle);
110 PUSH_DATA (push, fifo->vram);
111 PUSH_DATA (push, fifo->gart);
113 PUSH_DATA (push, fifo->vram);
114 PUSH_DATA (push, fifo->vram);
116 PUSH_DATA (pus
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H A Dnv10_context.c156 PUSH_DATA (push, pack_zs_f(s->format, ctx->Depth.Clear, 0));
158 PUSH_DATA (push, 1);
210 PUSH_DATA (push, hw->eng3d->handle);
212 PUSH_DATA (push, hw->ntfy->handle);
215 PUSH_DATA (push, fifo->vram);
216 PUSH_DATA (push, fifo->gart);
217 PUSH_DATA (push, fifo->gart);
219 PUSH_DATA (push, fifo->vram);
220 PUSH_DATA (push, fifo->vram);
223 PUSH_DATA (pus
[all...]
H A Dnv20_state_frag.c43 PUSH_DATA (push, a_in);
45 PUSH_DATA (push, a_out);
47 PUSH_DATA (push, c_in);
49 PUSH_DATA (push, c_out);
51 PUSH_DATA (push, k);
66 PUSH_DATA (push, in);
67 PUSH_DATA (push, in >> 32);
70 PUSH_DATA (push, MAX2(1, n));
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nvc0/
H A Dnvc0_compute.c59 PUSH_DATA (push, screen->compute->oclass);
63 PUSH_DATA (push, screen->mp_count);
65 PUSH_DATA (push, 0xf);
68 PUSH_DATA (push, 0x8000);
72 PUSH_DATA (push, 0);
75 PUSH_DATA (push, (0xc << 28) | (i << 16) | i);
77 PUSH_DATA (push, 1);
82 PUSH_DATA (push, screen->tls->offset);
85 PUSH_DATA (push, screen->tls->size);
87 PUSH_DATA (pus
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nvc0/
H A Dnvc0_compute.c59 PUSH_DATA (push, screen->compute->oclass);
63 PUSH_DATA (push, screen->mp_count);
65 PUSH_DATA (push, 0xf);
68 PUSH_DATA (push, 0x8000);
72 PUSH_DATA (push, 0);
75 PUSH_DATA (push, (0xc << 28) | (i << 16) | i);
77 PUSH_DATA (push, 1);
82 PUSH_DATA (push, screen->tls->offset);
85 PUSH_DATA (push, screen->tls->size);
87 PUSH_DATA (pus
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nv50/
H A Dnv50_compute.c71 PUSH_DATA (push, screen->compute->handle);
74 PUSH_DATA (push, 1);
76 PUSH_DATA (push, fifo->vram);
79 PUSH_DATA (push, screen->stack_bo->offset);
81 PUSH_DATA (push, 4);
84 PUSH_DATA (push, 1);
86 PUSH_DATA (push, 1);
88 PUSH_DATA (push, NV50_COMPUTE_REG_MODE_STRIPED);
90 PUSH_DATA (push, 0x100);
92 PUSH_DATA (pus
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nv30/
H A Dnv30_clear.c79 PUSH_DATA (push, 0);
80 PUSH_DATA (push, 0x000000ff);
88 PUSH_DATA (push, zeta);
89 PUSH_DATA (push, colr);
90 PUSH_DATA (push, mode);
94 PUSH_DATA (push, zeta);
95 PUSH_DATA (push, colr);
96 PUSH_DATA (push, mode);
136 PUSH_DATA (push, NV30_3D_RT_ENABLE_COLOR0);
138 PUSH_DATA (pus
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H A Dnv30_transfer.c93 PUSH_DATA (push, vp->start);
95 PUSH_DATA (push, 0x401f9c6c); /* mov o[hpos], a[0]; */
96 PUSH_DATA (push, 0x0040000d);
97 PUSH_DATA (push, 0x8106c083);
98 PUSH_DATA (push, 0x6041ff80);
100 PUSH_DATA (push, 0x401f9c6c); /* mov o[tex0], a[8]; end; */
101 PUSH_DATA (push, 0x0040080d);
102 PUSH_DATA (push, 0x8106c083);
103 PUSH_DATA (push, 0x6041ff9d);
199 PUSH_DATA (pus
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nv30/
H A Dnv30_clear.c79 PUSH_DATA (push, 0);
80 PUSH_DATA (push, 0x000000ff);
88 PUSH_DATA (push, zeta);
89 PUSH_DATA (push, colr);
90 PUSH_DATA (push, mode);
94 PUSH_DATA (push, zeta);
95 PUSH_DATA (push, colr);
96 PUSH_DATA (push, mode);
136 PUSH_DATA (push, NV30_3D_RT_ENABLE_COLOR0);
138 PUSH_DATA (pus
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H A Dnv30_transfer.c93 PUSH_DATA (push, vp->start);
95 PUSH_DATA (push, 0x401f9c6c); /* mov o[hpos], a[0]; */
96 PUSH_DATA (push, 0x0040000d);
97 PUSH_DATA (push, 0x8106c083);
98 PUSH_DATA (push, 0x6041ff80);
100 PUSH_DATA (push, 0x401f9c6c); /* mov o[tex0], a[8]; end; */
101 PUSH_DATA (push, 0x0040080d);
102 PUSH_DATA (push, 0x8106c083);
103 PUSH_DATA (push, 0x6041ff9d);
199 PUSH_DATA (pus
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