Searched refs:REG_TYPE (Results 1 - 8 of 8) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_3d.h299 #define REG_TYPE(reg) (((reg) >> REG_TYPE_SHIFT) & REG_TYPE_MASK) macro
360 (REG_TYPE(reg) << D0_TYPE_SHIFT) | \
362 ((REG_TYPE(reg) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0)); \
370 (REG_TYPE(dest_reg) << T0_DEST_TYPE_SHIFT) | \
373 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
381 (REG_TYPE(dest_reg) << T0_DEST_TYPE_SHIFT) | \
384 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
399 (REG_TYPE(dest_reg) << A0_DEST_TYPE_SHIFT) | \
404 (REG_TYPE(operand0) << A0_SRC0_TYPE_SHIFT) | \
419 (REG_TYPE(operand
[all...]
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_3d.h299 #define REG_TYPE(reg) (((reg) >> REG_TYPE_SHIFT) & REG_TYPE_MASK) macro
360 (REG_TYPE(reg) << D0_TYPE_SHIFT) | \
362 ((REG_TYPE(reg) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0)); \
370 (REG_TYPE(dest_reg) << T0_DEST_TYPE_SHIFT) | \
373 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
381 (REG_TYPE(dest_reg) << T0_DEST_TYPE_SHIFT) | \
384 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
399 (REG_TYPE(dest_reg) << A0_DEST_TYPE_SHIFT) | \
404 (REG_TYPE(operand0) << A0_SRC0_TYPE_SHIFT) | \
419 (REG_TYPE(operand
[all...]
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di915_3d.h87 #define REG_TYPE(reg) ((reg) >> 8) macro
221 op.ui[0] = D0_DCL | (REG_TYPE(reg) << D0_TYPE_SHIFT) |
225 if (REG_TYPE(reg) != REG_TYPE_S)
253 if (REG_TYPE(sampler_reg) != REG_TYPE_S)
257 op.ui[0] |= REG_TYPE(dest_reg) << T0_DEST_TYPE_SHIFT;
260 op.ui[1] |= REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT;
283 op.ui[0] |= REG_TYPE(dest_reg) << A0_DEST_TYPE_SHIFT;
288 op.ui[0] |= REG_TYPE(operand0.reg) << A0_SRC0_TYPE_SHIFT;
312 op.ui[1] |= REG_TYPE(operand1.reg) << A1_SRC1_TYPE_SHIFT;
336 op.ui[2] |= REG_TYPE(operand
[all...]
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen3_render.h1146 #define REG_TYPE(reg) (((reg) >> REG_TYPE_SHIFT) & REG_TYPE_MASK) macro
1207 (REG_TYPE(reg) << D0_TYPE_SHIFT) | \
1209 ((REG_TYPE(reg) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0)); \
1217 (REG_TYPE(dest_reg) << T0_DEST_TYPE_SHIFT) | \
1220 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
1228 (REG_TYPE(dest_reg) << T0_DEST_TYPE_SHIFT) | \
1231 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
1246 (REG_TYPE(dest_reg) << A0_DEST_TYPE_SHIFT) | \
1251 (REG_TYPE(operand0) << A0_SRC0_TYPE_SHIFT) | \
1266 (REG_TYPE(operand
[all...]
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen3_render.h1146 #define REG_TYPE(reg) (((reg) >> REG_TYPE_SHIFT) & REG_TYPE_MASK) macro
1207 (REG_TYPE(reg) << D0_TYPE_SHIFT) | \
1209 ((REG_TYPE(reg) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0)); \
1217 (REG_TYPE(dest_reg) << T0_DEST_TYPE_SHIFT) | \
1220 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
1228 (REG_TYPE(dest_reg) << T0_DEST_TYPE_SHIFT) | \
1231 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
1246 (REG_TYPE(dest_reg) << A0_DEST_TYPE_SHIFT) | \
1251 (REG_TYPE(operand0) << A0_SRC0_TYPE_SHIFT) | \
1266 (REG_TYPE(operand
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_inst.h251 #define REG_TYPE(reg) \ macro
268 REG_TYPE(dst)
269 REG_TYPE(src)
270 #undef REG_TYPE
309 #define REG_TYPE(reg) \ macro
337 REG_TYPE(dst)
338 REG_TYPE(src0)
339 REG_TYPE(src1)
340 REG_TYPE(src2)
341 #undef REG_TYPE
900 #define REG_TYPE macro
924 REG_TYPE(src0) function in typeref:typename:dst
[all...]
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_inst.h380 #define REG_TYPE(reg) \ macro
397 REG_TYPE(dst)
398 REG_TYPE(src)
399 #undef REG_TYPE
442 #define REG_TYPE(reg) \ macro
470 REG_TYPE(dst)
471 REG_TYPE(src0)
472 REG_TYPE(src1)
473 REG_TYPE(src2)
474 #undef REG_TYPE
1164 #define REG_TYPE macro
1188 REG_TYPE(src0) function in typeref:typename:dst
[all...]
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D20.0.0.rst2508 - intel/compiler: Add a INVALID_{,HW_}REG_TYPE macros

Completed in 17 milliseconds